From: shuang.he@intel.com
To: shuang.he@intel.com, lei.a.liu@intel.com,
intel-gfx@lists.freedesktop.org, ville.syrjala@linux.intel.com
Subject: Re: [PATCH 3/3] drm/i915: Drop the 64k linear scanout alignment on gen2/3
Date: 14 Jun 2015 16:18:29 -0700 [thread overview]
Message-ID: <c45ac1$hgg5ds@orsmga003.jf.intel.com> (raw)
In-Reply-To: <1434029476-958-3-git-send-email-ville.syrjala@linux.intel.com>
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 6570
-------------------------------------Summary-------------------------------------
Platform Delta drm-intel-nightly Series Applied
PNV 276/276 276/276
ILK 303/303 303/303
SNB 312/312 312/312
IVB 343/343 343/343
BYT 287/287 287/287
BDW 321/321 321/321
-------------------------------------Detailed-------------------------------------
Platform Test drm-intel-nightly Series Applied
Note: You need to pay more attention to line start with '*'
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next prev parent reply other threads:[~2015-06-14 23:18 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-06-11 13:31 [PATCH 1/3] drm/i915: Actually respect DSPSURF alignment restrictions ville.syrjala
2015-06-11 13:31 ` [PATCH 2/3] drm/i915: Align DSPSURF to 128k on VLV/CHV ville.syrjala
2015-06-12 0:46 ` Clint Taylor
2015-06-12 4:47 ` Arun R Murthy
2015-06-11 13:31 ` [PATCH 3/3] drm/i915: Drop the 64k linear scanout alignment on gen2/3 ville.syrjala
2015-06-11 13:52 ` Chris Wilson
2015-06-14 23:18 ` shuang.he [this message]
2015-06-11 13:51 ` [PATCH 1/3] drm/i915: Actually respect DSPSURF alignment restrictions Chris Wilson
2015-06-12 10:50 ` Ville Syrjälä
2015-06-15 16:04 ` Daniel Vetter
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