From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chris Wilson Subject: Re: [PATCH] intel: Fix emit_linear_blit to use DWORD aligned width blits Date: Tue, 09 Nov 2010 11:43:58 +0000 Message-ID: References: <1289037871.2453.3.camel@pcjc2lap> <5b55a1$ijc3pt@fmsmga002.fm.intel.com> <1289299956.2999.8.camel@pcjc2lap> <1289302492.2999.16.camel@pcjc2lap> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTP id ADFC09E733 for ; Tue, 9 Nov 2010 03:44:02 -0800 (PST) In-Reply-To: <1289302492.2999.16.camel@pcjc2lap> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Peter Clifton Cc: "intel-gfx@lists.freedesktop.org" List-Id: intel-gfx@lists.freedesktop.org On Tue, 09 Nov 2010 11:34:52 +0000, Peter Clifton wrote: > On Tue, 2010-11-09 at 10:52 +0000, Peter Clifton wrote: > > On Sun, 2010-11-07 at 10:25 +0000, Chris Wilson wrote: > > > I've not tried that yet, but the PRM does state that BLT pitch is in > > DWORDs. > > Gah.. the PRM is badly written in places! In one place it states DWORDs, > then in another you get the actual detail: Of course, I was reading another document which made no mention of the tiling or dword restrictions ;-) Contradictory, uncrossreferenced, incomplete docs are all we have. > Chris, I can try word-aligned if you wish, but am chasing some other > random GPU hangs / crashes at the moment. Fun fun ;) No need, life is too short. > (PS. Any idea where batchbuffer containing 3D commands, but with a > string of 6-8 MI_NOOP commands would come from? I can't find code to > emit like that in MESA or the 2D driver - I am wondering if the buffer > had become corrupted). Keep digging and you'll find a reference to some silicon bugs for which certain commands (in this case it's probably the URB_FENCE) must not cross cache-lines. I'm guessing that the MI_NOOPs you've seen are due to us aligning the following commands to meet such constraints. -Chris -- Chris Wilson, Intel Open Source Technology Centre