Re: [PATCH v2 1/1] drm/i915: Do RPM Wake during GuC/HuC status read

Arkadiusz Hiler
2017-02-07T13:20:22Z

On Mon, Feb 06, 2017 at 10:34:31AM +0530, Kamble, Sagar A wrote:
>
>
> On 2/4/2017 7:40 PM, Arkadiusz Hiler wrote:
> > On Fri, Feb 03, 2017 at 01:58:33PM +0530, Sagar Arun Kamble wrote:
> > > HUC_STATUS, GUC_STATUS, SOFT_SCRATCH registers are read in debugfs
> > > and getparam ioctl. This patch covers those accesses by RPM get/put.
> > >
> > > v2: Covering access in i915_getparam(I915_PARAM_HUC_STATUS) (ChrisW)
> > >
> > > Cc: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
> > > Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
> > > Cc: Fiedorowicz, Lukasz <lukasz.fiedorowicz@intel.com>
> > > Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/i915_debugfs.c | 6 ++++++
> > > drivers/gpu/drm/i915/i915_drv.c | 5 ++---
> > > 2 files changed, 8 insertions(+), 3 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> > > index 3ae0656..639ed12 100644
> > > --- a/drivers/gpu/drm/i915/i915_debugfs.c
> > > +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> > > @@ -2374,7 +2374,9 @@ static int i915_huc_load_status_info(struct seq_file *m, void *data)
> > > seq_printf(m, "\tRSA: offset is %d; size = %d\n",
> > > huc_fw->rsa_offset, huc_fw->rsa_size);
> > > + intel_runtime_pm_get(dev_priv);
> > > seq_printf(m, "\nHuC status 0x%08x:\n", I915_READ(HUC_STATUS2));
> > > + intel_runtime_pm_put(dev_priv);
> > > return 0;
> > > }
> > Are you sure that HUC_STATUS2 requires RPM get for reading?
> >
> > I remember trying reading it with device forcefully asleep and it
> > succeed just fine.
> Hi Arek,
>
> Faced following warning with device runtime_status=suspended.
> Also this register lies in media forcewake range and should have similar RPM
> get/put needs as other registers unless this has special behavior I am not
> aware of.

Reviewed-by: Arkadiusz Hiler <arkadiusz.hiler@intel.com>

--
Cheers,
Arek