From: "Nautiyal, Ankit K" <ankit.k.nautiyal@intel.com>
To: Jani Nikula <jani.nikula@linux.intel.com>,
<intel-gfx@lists.freedesktop.org>,
<intel-xe@lists.freedesktop.org>
Cc: <ville.syrjala@linux.intel.com>
Subject: Re: [PATCH 07/15] drm/i915/psr: Add function to compute max link-wake latency
Date: Tue, 5 Aug 2025 11:57:44 +0530 [thread overview]
Message-ID: <c8b29417-b10a-4b51-b439-4204e114e710@intel.com> (raw)
In-Reply-To: <274c7d61358d9355708971d66c444d4662851f4d@intel.com>
On 8/5/2025 2:24 AM, Jani Nikula wrote:
> On Mon, 04 Aug 2025, Ankit Nautiyal <ankit.k.nautiyal@intel.com> wrote:
>> Introduce a helper to compute the max link wake latency when using
>> Auxless/Aux wake mechanism for PSR/Panel Replay/LOBF features.
>>
>> This will be used to compute the minimum guardband so that the link wake
>> latencies are accounted and these features work smoothly for higher
>> refresh rate panels.
>>
>> Bspec: 70151, 71477
>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>> ---
>> drivers/gpu/drm/i915/display/intel_psr.c | 64 ++++++++++++++++++++++++
>> drivers/gpu/drm/i915/display/intel_psr.h | 3 ++
>> 2 files changed, 67 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
>> index 6bd3454bb00e..6cdaff3ccc9f 100644
>> --- a/drivers/gpu/drm/i915/display/intel_psr.c
>> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
>> @@ -33,6 +33,7 @@
>> #include "intel_atomic.h"
>> #include "intel_crtc.h"
>> #include "intel_cursor_regs.h"
>> +#include "intel_cx0_phy.h"
>> #include "intel_ddi.h"
>> #include "intel_de.h"
>> #include "intel_display_irq.h"
>> @@ -4249,3 +4250,66 @@ bool intel_psr_needs_alpm_aux_less(struct intel_dp *intel_dp,
>> {
>> return intel_dp_is_edp(intel_dp) && crtc_state->has_panel_replay;
>> }
>> +
>> +static
>> +int intel_psr_compute_aux_wake_latency(struct intel_dp *intel_dp,
>> + struct intel_crtc_state *crtc_state)
>> +{
>> +#define TFW_EXIT_LATENCY_MS 20000
>> +#define FAST_WAKE_LATENCY_MS 12000 /* Preamble: 8us; PHY wake: 4us */
>> + struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
>> + int aux_wake_latency_us;
>> + int io_buffer_wake_ms;
>> +
>> + io_buffer_wake_ms = intel_encoder_is_c10phy(encoder) ? 9790 : 14790;
>> +
>> + aux_wake_latency_us =
>> + DIV_ROUND_UP(io_buffer_wake_ms + TFW_EXIT_LATENCY_MS + FAST_WAKE_LATENCY_MS, 1000);
> See https://lore.kernel.org/r/eeda84457c813151a3459a46a91946b4fbbb9e44@intel.com
Oops! I think I have messed up msecs and usecs in the calculations.
I have realized, part of these calculations are already there in
functions in intel_alpm.c which can be used here.
I will correct this and rework on the patch.
Thanks Jani, for pointing this out.
Regards,
Ankit
>
>> +
>> + return aux_wake_latency_us;
>> +}
>> +
>> +static
>> +int intel_psr_compute_auxless_latency(struct intel_crtc_state *crtc_state)
>> +{
>> +#define PHY_ESTABLISHMENT_PERIOD_MS 50000
>> +#define LFPS_PERIOD_MS 800
>> +#define SILENCE_MAX_MS 180
>> + int linkrate_mhz = crtc_state->port_clock / 1000;
>> + int clock_data_switch_ms;
>> + int auxless_latency_us;
>> + int time_ml_phy_lock_ms;
>> + int num_ml_phy_lock;
>> + /*
>> + * TPS4 length = 252
>> + * tML_PHY_LOCK = TPS4 Length * ( 10 / (Link Rate in MHz) )
>> + * Number ML_PHY_LOCK = ( 7 + CEILING(6.5us / tML_PHY_LOCK ) + 1)
>> + * t2 = Number ML_PHY_LOCK * tML_PHY_LOCK
>> + * tCDS term = 2 * t2
>> + * =>tCDS_term = 2 * (7 * (252 * (10 /linkrate))+6.5)
>> + */
>> + time_ml_phy_lock_ms = (1000 * 252 * 10) / linkrate_mhz;
>> + num_ml_phy_lock = 7 + DIV_ROUND_UP(6500 * 1000, time_ml_phy_lock_ms) / 1000 + 1;
>> + clock_data_switch_ms = 2 * time_ml_phy_lock_ms * num_ml_phy_lock;
>> +
>> + auxless_latency_us = (LFPS_PERIOD_MS + SILENCE_MAX_MS + PHY_ESTABLISHMENT_PERIOD_MS +
>> + clock_data_switch_ms) / 1000;
>> +
>> + return auxless_latency_us;
>> +}
>> +
>> +int intel_psr_compute_max_link_wake_latency(struct intel_dp *intel_dp,
>> + struct intel_crtc_state *crtc_state,
>> + bool assume_all_enabled)
>> +{
>> + int aux_wake_latency = 0;
>> + int auxless_latency = 0;
>> +
>> + if (assume_all_enabled || crtc_state->has_sel_update)
>> + auxless_latency = intel_psr_compute_aux_wake_latency(intel_dp, crtc_state);
>> +
>> + if (assume_all_enabled || crtc_state->has_panel_replay)
>> + aux_wake_latency = intel_psr_compute_auxless_latency(crtc_state);
>> +
>> + return max(auxless_latency, aux_wake_latency);
>> +}
>> diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h
>> index 9b061a22361f..c58d29620b49 100644
>> --- a/drivers/gpu/drm/i915/display/intel_psr.h
>> +++ b/drivers/gpu/drm/i915/display/intel_psr.h
>> @@ -81,5 +81,8 @@ void intel_psr_debugfs_register(struct intel_display *display);
>> bool intel_psr_needs_alpm(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state);
>> bool intel_psr_needs_alpm_aux_less(struct intel_dp *intel_dp,
>> const struct intel_crtc_state *crtc_state);
>> +int intel_psr_compute_max_link_wake_latency(struct intel_dp *intel_dp,
>> + struct intel_crtc_state *crtc_state,
>> + bool assume_all_enabled);
>>
>> #endif /* __INTEL_PSR_H__ */
next prev parent reply other threads:[~2025-08-05 6:27 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-08-04 13:24 [PATCH 00/15] Optimize vrr.guardband and fix LRR Ankit Nautiyal
2025-08-04 13:24 ` [PATCH 01/15] drm/i915/skl_watermark: Fix the scaling factor for chroma subsampling Ankit Nautiyal
2025-08-04 13:24 ` [PATCH 02/15] drm/i915/skl_watermark: Add bounds check for scaler array access Ankit Nautiyal
2025-08-04 13:24 ` [PATCH 03/15] drm/i915/skl_watermark: Pass linetime as argument to latency helpers Ankit Nautiyal
2025-08-04 13:24 ` [PATCH 04/15] drm/i915/skl_scaler: Introduce helper for chroma downscale factor Ankit Nautiyal
2025-08-04 13:24 ` [PATCH 05/15] drm/i915/display: Extract helpers to set dsc/scaler prefill latencies Ankit Nautiyal
2025-08-04 13:24 ` [PATCH 06/15] drm/i915/dp: Add SDP latency computation helper Ankit Nautiyal
2025-08-04 13:24 ` [PATCH 07/15] drm/i915/psr: Add function to compute max link-wake latency Ankit Nautiyal
2025-08-04 20:54 ` Jani Nikula
2025-08-05 6:27 ` Nautiyal, Ankit K [this message]
2025-08-04 13:24 ` [PATCH 08/15] drm/i915/psr: Store max PSR2/Panel Replay latency in crtc_state Ankit Nautiyal
2025-08-04 13:24 ` [PATCH 09/15] drm/i915/vrr: Use vrr.sync_start for getting vtotal Ankit Nautiyal
2025-08-04 13:24 ` [PATCH 10/15] drm/i915/display: Add guardband check for feature latencies Ankit Nautiyal
2025-08-04 13:24 ` [PATCH 11/15] drm/i915/skl_watermark: Remove redundant latency checks from vblank validation Ankit Nautiyal
2025-08-04 13:24 ` [PATCH 12/15] drm/i915/vrr: Use static guardband to support seamless LRR switching Ankit Nautiyal
2025-08-04 13:24 ` [PATCH 13/15] drm/i915/vrr: Set vrr.vmin to min Vtotal Ankit Nautiyal
2025-08-04 13:24 ` [PATCH 14/15] drm/i915/panel: Add helper to get highest fixed mode Ankit Nautiyal
2025-08-04 13:24 ` [PATCH 15/15] drm/i915/vrr: Fix seamless_mn drrs for PTL Ankit Nautiyal
2025-08-04 14:42 ` ✓ i915.CI.BAT: success for Optimize vrr.guardband and fix LRR (rev2) Patchwork
2025-08-05 2:14 ` ✓ i915.CI.Full: " Patchwork
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=c8b29417-b10a-4b51-b439-4204e114e710@intel.com \
--to=ankit.k.nautiyal@intel.com \
--cc=intel-gfx@lists.freedesktop.org \
--cc=intel-xe@lists.freedesktop.org \
--cc=jani.nikula@linux.intel.com \
--cc=ville.syrjala@linux.intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).