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Some bit > manipulation is needed because of the format of PKG_PWR_LIM_1_TIME in > GT0_PACKAGE_RAPL_LIMIT register (1.x * power(2,y)). > > v2: Update date and kernel version in Documentation (Badal) > v3: Cleaned up hwm_power1_max_interval_store() (Badal) > > Signed-off-by: Ashutosh Dixit > Signed-off-by: Badal Nilawar > Acked-by: Guenter Roeck > --- > .../ABI/testing/sysfs-driver-intel-i915-hwmon | 9 ++ > drivers/gpu/drm/i915/i915_hwmon.c | 114 +++++++++++++++++- > drivers/gpu/drm/i915/i915_reg.h | 3 + > drivers/gpu/drm/i915/intel_mchbar_regs.h | 4 + > 4 files changed, 129 insertions(+), 1 deletion(-) > > diff --git a/Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon b/Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon > index cc70596fff44..7995a885c9d6 100644 > --- a/Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon > +++ b/Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon > @@ -26,6 +26,15 @@ Description: RO. Card default power limit (default TDP setting). > > Only supported for particular Intel i915 graphics platforms. > > +What: /sys/devices/.../hwmon/hwmon/power1_max_interval > +Date: September 2022 > +KernelVersion: 6 > +Contact: dri-devel@lists.freedesktop.org > +Description: RW. Sustained power limit interval (Tau in PL1/Tau) in > + milliseconds over which sustained power is averaged. > + > + Only supported for particular Intel i915 graphics platforms. > + > What: /sys/devices/.../hwmon/hwmon/power1_crit > Date: September 2022 > KernelVersion: 6 > diff --git a/drivers/gpu/drm/i915/i915_hwmon.c b/drivers/gpu/drm/i915/i915_hwmon.c > index bd9ba312c474..7d85a81bc39b 100644 > --- a/drivers/gpu/drm/i915/i915_hwmon.c > +++ b/drivers/gpu/drm/i915/i915_hwmon.c > @@ -20,11 +20,13 @@ > * - power - microwatts > * - curr - milliamperes > * - energy - microjoules > + * - time - milliseconds > */ > #define SF_VOLTAGE 1000 > #define SF_POWER 1000000 > #define SF_CURR 1000 > #define SF_ENERGY 1000000 > +#define SF_TIME 1000 > > struct hwm_reg { > i915_reg_t gt_perf_status; > @@ -53,6 +55,7 @@ struct i915_hwmon { > struct hwm_reg rg; > int scl_shift_power; > int scl_shift_energy; > + int scl_shift_time; > }; > > static void > @@ -161,6 +164,114 @@ hwm_energy(struct hwm_drvdata *ddat, long *energy) > return 0; > } > > +static ssize_t > +hwm_power1_max_interval_show(struct device *dev, struct device_attribute *attr, > + char *buf) > +{ > + struct hwm_drvdata *ddat = dev_get_drvdata(dev); > + struct i915_hwmon *hwmon = ddat->hwmon; > + intel_wakeref_t wakeref; > + u32 r, x, y, x_w = 2; /* 2 bits */ > + u64 tau4, out; > + > + with_intel_runtime_pm(ddat->uncore->rpm, wakeref) > + r = intel_uncore_read(ddat->uncore, hwmon->rg.pkg_rapl_limit); > + > + x = REG_FIELD_GET(PKG_PWR_LIM_1_TIME_X, r); > + y = REG_FIELD_GET(PKG_PWR_LIM_1_TIME_Y, r); > + /* > + * tau = 1.x * power(2,y), x = bits(23:22), y = bits(21:17) > + * = (4 | x) << (y - 2) > + * where (y - 2) ensures a 1.x fixed point representation of 1.x > + * However because y can be < 2, we compute > + * tau4 = (4 | x) << y > + * but add 2 when doing the final right shift to account for units > + */ > + tau4 = ((1 << x_w) | x) << y; > + /* val in hwmon interface units (millisec) */ > + out = mul_u64_u32_shr(tau4, SF_TIME, hwmon->scl_shift_time + x_w); > + > + return sysfs_emit(buf, "%llu\n", out); > +} > + > +static ssize_t > +hwm_power1_max_interval_store(struct device *dev, > + struct device_attribute *attr, > + const char *buf, size_t count) > +{ > + struct hwm_drvdata *ddat = dev_get_drvdata(dev); > + struct i915_hwmon *hwmon = ddat->hwmon; > + long val, max_win, ret; > + u32 x, y, rxy, x_w = 2; /* 2 bits */ > + u64 tau4, r; > + > +#define PKG_MAX_WIN_DEFAULT 0x12ull > + > + ret = kstrtoul(buf, 0, &val); > + if (ret) > + return ret; > + > + /* > + * val must be < max in hwmon interface units. The steps below are > + * explained in i915_power1_max_interval_show() > + */ > + r = FIELD_PREP(PKG_MAX_WIN, PKG_MAX_WIN_DEFAULT); AFAIU we need to read r from PACKAGE_POWER_SKU reg untill unless it has some known issue? > + x = REG_FIELD_GET(PKG_MAX_WIN_X, r); > + y = REG_FIELD_GET(PKG_MAX_WIN_Y, r); > + tau4 = ((1 << x_w) | x) << y; > + max_win = mul_u64_u32_shr(tau4, SF_TIME, hwmon->scl_shift_time + x_w); > + > + if (val > max_win) > + return -EINVAL; > + > + /* val in hw units */ > + val = DIV_ROUND_CLOSEST_ULL((u64)val << hwmon->scl_shift_time, SF_TIME); > + /* Convert to 1.x * power(2,y) */ > + if (!val) > + return -EINVAL; > + y = ilog2(val); > + /* x = (val - (1 << y)) >> (y - 2); */ > + x = (val - (1ul << y)) << x_w >> y; > + > + rxy = REG_FIELD_PREP(PKG_PWR_LIM_1_TIME_X, x) | REG_FIELD_PREP(PKG_PWR_LIM_1_TIME_Y, y); > + > + hwm_locked_with_pm_intel_uncore_rmw(ddat, hwmon->rg.pkg_rapl_limit, > + PKG_PWR_LIM_1_TIME, rxy); > + return count; > +} > + /snip > if (IS_ERR(hwmon_dev)) { > mutex_destroy(&hwmon->hwmon_lock); > i915->hwmon = NULL; > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 956e5298ef1e..68e7cc85dc53 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -1811,6 +1811,9 @@ > * *_PACKAGE_POWER_SKU - SKU power and timing parameters. > */ > #define PKG_PKG_TDP GENMASK_ULL(14, 0) > +#define PKG_MAX_WIN GENMASK_ULL(54, 48) > +#define PKG_MAX_WIN_X GENMASK_ULL(54, 53) > +#define PKG_MAX_WIN_Y GENMASK_ULL(52, 48) These GENMASK fields needs a reg definition. Br, Anshuman Gupta. > > #define CHV_CLK_CTL1 _MMIO(0x101100) > #define VLV_CLK_CTL2 _MMIO(0x101104) > diff --git a/drivers/gpu/drm/i915/intel_mchbar_regs.h b/drivers/gpu/drm/i915/intel_mchbar_regs.h > index 1014d0b7cc16..9331a3c15fd1 100644 > --- a/drivers/gpu/drm/i915/intel_mchbar_regs.h > +++ b/drivers/gpu/drm/i915/intel_mchbar_regs.h > @@ -206,6 +206,10 @@ > #define RPE_MASK REG_GENMASK(15, 8) > #define PCU_PACKAGE_RAPL_LIMIT _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x59a0) > #define PKG_PWR_LIM_1 REG_GENMASK(14, 0) > +#define PKG_PWR_LIM_1_EN REG_BIT(15) > +#define PKG_PWR_LIM_1_TIME REG_GENMASK(23, 17) > +#define PKG_PWR_LIM_1_TIME_X REG_GENMASK(23, 22) > +#define PKG_PWR_LIM_1_TIME_Y REG_GENMASK(21, 17) > > /* snb MCH registers for priority tuning */ > #define MCH_SSKPD _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5d10)