From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C55A5C433FE for ; Tue, 8 Feb 2022 10:20:35 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 84DAF10E5EC; Tue, 8 Feb 2022 10:20:33 +0000 (UTC) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTPS id DE17510E5A9; Tue, 8 Feb 2022 10:20:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1644315631; x=1675851631; h=message-id:date:mime-version:subject:to:cc:references: from:in-reply-to:content-transfer-encoding; bh=QR/FGcjZGeFX/ZbBbenaXNWwLhYv6QtpxCSe6+NHh4g=; b=RCRt14Y5lVE/A/W0NEF5L90TPDrH66bAGixSSHFc+qKMJ7XjfDmIdfwg yKJ5wVU98fVv7qJTdMXFCPNx5ukJL0p66GxqKdrwdNHegYCBfwBmk6Lps nPoq2ddZNoo/90EqryKvDDjiBcF6zasJ6c2GVgvRxsYStbA7aNb/kt6YI XXIMxuIZVNxSEg5OIc7GtZdJeoSuCIRRX5J/23UYsE3Ckjfk9WP1ZFg8a zk/4+Trdn7tIk+XltHR8PyOPUbRSjBh0AGfVbOgyWuvJQHS9+0F7HJIhg SMMkDQ6DfCRFu363WA7vr4uWgsPbineuY5/6Lk17hYfoerTwpGz1C/xVB g==; X-IronPort-AV: E=McAfee;i="6200,9189,10251"; a="249127140" X-IronPort-AV: E=Sophos;i="5.88,352,1635231600"; d="scan'208";a="249127140" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Feb 2022 02:20:31 -0800 X-IronPort-AV: E=Sophos;i="5.88,352,1635231600"; d="scan'208";a="525497170" Received: from kgonza2-mobl2.gar.corp.intel.com (HELO [10.213.198.226]) ([10.213.198.226]) by orsmga007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Feb 2022 02:20:29 -0800 Message-ID: Date: Tue, 8 Feb 2022 10:20:26 +0000 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.5.0 Content-Language: en-US To: Michael Cheng , intel-gfx@lists.freedesktop.org References: <20220207201127.648624-1-michael.cheng@intel.com> <20220207201127.648624-7-michael.cheng@intel.com> From: Tvrtko Ursulin Organization: Intel Corporation UK Plc In-Reply-To: <20220207201127.648624-7-michael.cheng@intel.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Subject: Re: [Intel-gfx] [PATCH v6 6/6] drm: Add arch arm64 for drm_clflush_virt_range X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lucas.demarchi@intel.com, dri-devel@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On 07/02/2022 20:11, Michael Cheng wrote: > Use flush_tlb_kernel_range when invoking drm_clflush_virt_range on > arm64 platforms. Using flush_tlb_kernel_range will: > > 1. Make sure prior page-table updates have been completed > 2. Invalidate the TLB > 3. Check if the TLB invalidation has been completed Arm does not have a clflush equivalent but invalidating TLBs there includes flushing caches? Regards, Tvrtko > Signed-off-by: Michael Cheng > --- > drivers/gpu/drm/drm_cache.c | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/drivers/gpu/drm/drm_cache.c b/drivers/gpu/drm/drm_cache.c > index f19d9acbe959..d2506060a7c8 100644 > --- a/drivers/gpu/drm/drm_cache.c > +++ b/drivers/gpu/drm/drm_cache.c > @@ -176,6 +176,10 @@ drm_clflush_virt_range(void *addr, unsigned long length) > > if (wbinvd_on_all_cpus()) > pr_err("Timed out waiting for cache flush\n"); > + > +#elif defined(CONFIG_ARM64) > + void *end = addr + length; > + flush_tlb_kernel_range(*addr, *end); > #else > pr_err("Architecture has no drm_cache.c support\n"); > WARN_ON_ONCE(1);