Re: [PATCH v2 1/2] drm/i915/icl: Avoid Gen10 watermark workarounds in Gen11

Paulo Zanoni
2018-10-11T17:48:58Z

Em Qua, 2018-09-05 às 16:41 -0700, Rodrigo Vivi escreveu:
> On Wed, Sep 05, 2018 at 02:32:38PM +0530, Karthik B S wrote:
> > Display Workarounds #1125 and #1126 are intended for Gen10 and
> > below platforms. These workarounds can be avoided in Gen11.
> >
> > The result blocks for WM1-WM7 should be atleast as high as the
> > level below
> > the current level(Part of Display WA #1125). This part is
> > applicable even
> > for Gen11, so it is taken out of the condition check.
> >
> > v2: Improved Commit Message and addresed other review
> > comments(Rodrigo).
> >
>
> Cc: José Roberto de Souza <jose.souza@intel.com>
> > Signed-off-by: Karthik B S <karthik.b.s@intel.com>
>
>
> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> (but before pushing I'd like to get an ack from Jose since CI is not
> there yet with ICL)

Sorry, I didn't look at this patch earlier.

My understanding is that we also want to avoid this code in Gen10 since
only early CNL wants it, and GLK doesn't want it.

See https://patchwork.freedesktop.org/patch/254881/

>
> > ---
> > drivers/gpu/drm/i915/intel_pm.c | 37 +++++++++++++++++++++------
> > ----------
> > 1 file changed, 21 insertions(+), 16 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c
> > b/drivers/gpu/drm/i915/intel_pm.c
> > index d99e5fa..b5db6a3 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -4677,26 +4677,31 @@ static int skl_compute_plane_wm(const
> > struct drm_i915_private *dev_priv,
> > res_lines = div_round_up_fixed16(selected_result,
> > wp-
> > >plane_blocks_per_line);
> >
> > - /* Display WA #1125: skl,bxt,kbl,glk */
> > - if (level == 0 && wp->rc_surface)
> > - res_blocks += fixed16_to_u32_round_up(wp-
> > >y_tile_minimum);
> > -
> > - /* Display WA #1126: skl,bxt,kbl,glk */
> > - if (level >= 1 && level <= 7) {
> > - if (wp->y_tiled) {
> > + if (INTEL_GEN(dev_priv) < 11) {
> > + /* Display WA #1125: skl,bxt,kbl,glk */
> > + if (level == 0 && wp->rc_surface)
> > res_blocks += fixed16_to_u32_round_up(
> > wp-
> > >y_tile_minimum);
> > - res_lines += wp->y_min_scanlines;
> > - } else {
> > - res_blocks++;
> > +
> > + /* Display WA #1126: skl,bxt,kbl,glk */
> > + if (level >= 1 && level <= 7) {
> > + if (wp->y_tiled) {
> > + res_blocks +=
> > fixed16_to_u32_round_up
> > + (wp-
> > >y_tile_minimum);
> > + res_lines += wp->y_min_scanlines;
> > + } else {
> > + res_blocks++;
> > + }
> > }
> > + }
> >
> > - /*
> > - * Make sure result blocks for higher latency
> > levels are atleast
> > - * as high as level below the current level.
> > - * Assumption in DDB algorithm optimization for
> > special cases.
> > - * Also covers Display WA #1125 for RC.
> > - */
> > + /*
> > + * Make sure result blocks for higher latency levels are
> > atleast
> > + * as high as level below the current level.
> > + * Assumption in DDB algorithm optimization for special
> > cases.
> > + * Also covers Display WA #1125 for RC.
> > + */
> > + if (level >= 1 && level <= 7) {
> > if (result_prev->plane_res_b > res_blocks)
> > res_blocks = result_prev->plane_res_b;
> > }
> > --
> > 2.7.4
> >
>
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