From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.2 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,HK_RANDOM_FROM,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS, USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id ABE06C433EF for ; Wed, 8 Sep 2021 14:01:44 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 7721C6113A for ; Wed, 8 Sep 2021 14:01:44 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 7721C6113A Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id F334D6E155; Wed, 8 Sep 2021 14:01:38 +0000 (UTC) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id 5E8A26E0EB; Wed, 8 Sep 2021 14:01:37 +0000 (UTC) X-IronPort-AV: E=McAfee;i="6200,9189,10100"; a="200019494" X-IronPort-AV: E=Sophos;i="5.85,278,1624345200"; d="scan'208";a="200019494" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Sep 2021 07:01:10 -0700 X-IronPort-AV: E=Sophos;i="5.85,278,1624345200"; d="scan'208";a="465641511" Received: from eoinwals-mobl.ger.corp.intel.com (HELO [10.213.233.175]) ([10.213.233.175]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Sep 2021 07:01:09 -0700 To: Matt Roper , intel-gfx@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org, Aravind Iddamsetty , Prasad Nallani References: <20210907171916.2548047-1-matthew.d.roper@intel.com> <20210907171916.2548047-7-matthew.d.roper@intel.com> From: Tvrtko Ursulin Organization: Intel Corporation UK Plc Message-ID: Date: Wed, 8 Sep 2021 15:01:08 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.11.0 MIME-Version: 1.0 In-Reply-To: <20210907171916.2548047-7-matthew.d.roper@intel.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Subject: Re: [Intel-gfx] [PATCH 6/8] drm/i915/xehp: Define context scheduling attributes in lrc descriptor X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On 07/09/2021 18:19, Matt Roper wrote: > In Dual Context mode the EUs are shared between render and compute > command streamers. The hardware provides a field in the lrc descriptor > to indicate the prioritization of the thread dispatch associated to the > corresponding context. > > The context priority is set to 'low' at creation time and relies on the > existing context priority to set it to low/normal/high. > > HSDES: 1604462009 > Bspec: 46145, 46260 > Original-patch-by: Michel Thierry > Cc: Tvrtko Ursulin > Signed-off-by: Aravind Iddamsetty > Signed-off-by: Prasad Nallani > Signed-off-by: Matt Roper > --- > drivers/gpu/drm/i915/gt/intel_engine_cs.c | 4 +++- > drivers/gpu/drm/i915/gt/intel_engine_types.h | 1 + > drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 6 +++++- > drivers/gpu/drm/i915/gt/intel_lrc.h | 10 ++++++++++ > drivers/gpu/drm/i915/i915_reg.h | 4 ++++ > 5 files changed, 23 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c > index b346b946602d..2f719f0ecac3 100644 > --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c > +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c > @@ -382,8 +382,10 @@ static int intel_engine_setup(struct intel_gt *gt, enum intel_engine_id id) > engine->props.preempt_timeout_ms = 0; > > /* features common between engines sharing EUs */ > - if (engine->class == RENDER_CLASS || engine->class == COMPUTE_CLASS) > + if (engine->class == RENDER_CLASS || engine->class == COMPUTE_CLASS) { > engine->flags |= I915_ENGINE_HAS_RCS_REG_STATE; > + engine->flags |= I915_ENGINE_HAS_EU_PRIORITY; > + } > > engine->defaults = engine->props; /* never to change again */ > > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h > index 30a0c69c36c8..00bf0296b28a 100644 > --- a/drivers/gpu/drm/i915/gt/intel_engine_types.h > +++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h > @@ -455,6 +455,7 @@ struct intel_engine_cs { > #define I915_ENGINE_REQUIRES_CMD_PARSER BIT(7) > #define I915_ENGINE_WANT_FORCED_PREEMPTION BIT(8) > #define I915_ENGINE_HAS_RCS_REG_STATE BIT(9) > +#define I915_ENGINE_HAS_EU_PRIORITY BIT(10) > unsigned int flags; > > /* > diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c > index 4c600c46414d..2b36ec7f3a04 100644 > --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c > +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c > @@ -662,9 +662,13 @@ static inline void execlists_schedule_out(struct i915_request *rq) > static u64 execlists_update_context(struct i915_request *rq) > { > struct intel_context *ce = rq->context; > - u64 desc = ce->lrc.desc; > + u64 desc; > u32 tail, prev; > > + desc = ce->lrc.desc; > + if (rq->engine->flags & I915_ENGINE_HAS_EU_PRIORITY) > + desc |= lrc_desc_priority(rq_prio(rq)); > + > /* > * WaIdleLiteRestore:bdw,skl > * > diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.h b/drivers/gpu/drm/i915/gt/intel_lrc.h > index 7f697845c4cf..d3f2096b3d51 100644 > --- a/drivers/gpu/drm/i915/gt/intel_lrc.h > +++ b/drivers/gpu/drm/i915/gt/intel_lrc.h > @@ -79,4 +79,14 @@ static inline u32 lrc_get_runtime(const struct intel_context *ce) > return READ_ONCE(ce->lrc_reg_state[CTX_TIMESTAMP]); > } > > +static inline u32 lrc_desc_priority(int prio) > +{ > + if (prio > I915_PRIORITY_NORMAL) > + return GEN12_CTX_PRIORITY_HIGH; > + else if (prio < I915_PRIORITY_NORMAL) > + return GEN12_CTX_PRIORITY_LOW; > + else > + return GEN12_CTX_PRIORITY_NORMAL; > +} > + > #endif /* __INTEL_LRC_H__ */ > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 0bb185ce9529..5b68c02c35af 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -4212,6 +4212,10 @@ enum { > #define GEN8_CTX_L3LLC_COHERENT (1 << 5) > #define GEN8_CTX_PRIVILEGE (1 << 8) > #define GEN8_CTX_ADDRESSING_MODE_SHIFT 3 > +#define GEN12_CTX_PRIORITY_MASK REG_GENMASK(10, 9) > +#define GEN12_CTX_PRIORITY_HIGH REG_FIELD_PREP(GEN12_CTX_PRIORITY_MASK, 2) > +#define GEN12_CTX_PRIORITY_NORMAL REG_FIELD_PREP(GEN12_CTX_PRIORITY_MASK, 1) > +#define GEN12_CTX_PRIORITY_LOW REG_FIELD_PREP(GEN12_CTX_PRIORITY_MASK, 0) > > #define GEN8_CTX_ID_SHIFT 32 > #define GEN8_CTX_ID_WIDTH 21 > Haven't checked bspec to check the bitfield but the mechanics look good. Reviewed-by: Tvrtko Ursulin Regards, Tvrtko