[PATCH 1/2] drm/i915/cnl: Add support slice/subslice/eu configs

[PATCH 1/2] drm/i915/cnl: Add support slice/subslice/eu configs

[Rodrigo Vivi]

From: Ben Widawsky <ben@bwidawsk.net>

Cannonlake Slice and Subslice information has changed.

This patch initially provided by Ben adds the proper sseu
initialization.

v2: This v2 done by Rodrigo includes:
    - Fix on Total slices count by avoiding [1][2] and [2][2].
    - Inclusion of EU Per Subslice.
    - Commit message.
v3: This v3 done by Rodrigo includes:
    - Handle all possible bits and extra fuse register.
    - Use INTEL_GEN macro.
    - Fully assume uniform distribution so remove union
      with eu_per_subslice and add proper the comment.
v4: This v4 done by Rodrigo includes:
    - Consider all bits available: 6 bits for slices [27:22]
      and 4 for subslices [21:18].
v5: This v5 done by Rodrigo includes:
    - sseu->subslice_mask = (1 << 4) - 1 - missed on previous
    versions and noticed by Oscar.

Cc: Oscar Mateo <oscar.mateo@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h          |  8 +++++++
 drivers/gpu/drm/i915/intel_device_info.c | 37 +++++++++++++++++++++++++++++++-
 2 files changed, 44 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 94b40a469afd..9f4b8faf2982 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2730,6 +2730,11 @@ enum i915_power_well_id {
 #define   GEN9_F2_SS_DIS_SHIFT		20
 #define   GEN9_F2_SS_DIS_MASK		(0xf << GEN9_F2_SS_DIS_SHIFT)
 
+#define   GEN10_F2_S_ENA_SHIFT		22
+#define   GEN10_F2_S_ENA_MASK		(0x3f << GEN10_F2_S_ENA_SHIFT)
+#define   GEN10_F2_SS_DIS_SHIFT		18
+#define   GEN10_F2_SS_DIS_MASK		(0xf << GEN10_F2_SS_DIS_SHIFT)
+
 #define GEN8_EU_DISABLE0		_MMIO(0x9134)
 #define   GEN8_EU_DIS0_S0_MASK		0xffffff
 #define   GEN8_EU_DIS0_S1_SHIFT		24
@@ -2745,6 +2750,9 @@ enum i915_power_well_id {
 
 #define GEN9_EU_DISABLE(slice)		_MMIO(0x9134 + (slice)*0x4)
 
+#define GEN10_EU_DISABLE3		_MMIO(0x9140)
+#define   GEN10_EU_DIS_SS_MASK		0xff
+
 #define GEN6_BSD_SLEEP_PSMI_CONTROL	_MMIO(0x12050)
 #define   GEN6_BSD_SLEEP_MSG_DISABLE	(1 << 0)
 #define   GEN6_BSD_SLEEP_FLUSH_DISABLE	(1 << 2)
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 43831b09b47a..d2e7ae61775d 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -82,6 +82,39 @@ void intel_device_info_dump(struct drm_i915_private *dev_priv)
 #undef PRINT_FLAG
 }
 
+static void gen10_sseu_info_init(struct drm_i915_private *dev_priv)
+{
+	struct sseu_dev_info *sseu = &mkwrite_device_info(dev_priv)->sseu;
+	const u32 fuse2 = I915_READ(GEN8_FUSE2);
+
+	sseu->slice_mask = (fuse2 & GEN10_F2_S_ENA_MASK) >>
+			    GEN10_F2_S_ENA_SHIFT;
+	sseu->subslice_mask = (1 << 4) - 1;
+	sseu->subslice_mask &= ~((fuse2 & GEN10_F2_SS_DIS_MASK) >>
+				 GEN10_F2_SS_DIS_SHIFT);
+
+	sseu->eu_total = hweight32(~I915_READ(GEN8_EU_DISABLE0));
+	sseu->eu_total += hweight32(~I915_READ(GEN8_EU_DISABLE1));
+	sseu->eu_total += hweight32(~I915_READ(GEN8_EU_DISABLE2));
+	sseu->eu_total += hweight8(~(I915_READ(GEN10_EU_DISABLE3) &
+				     GEN10_EU_DIS_SS_MASK));
+
+	/*
+	 * CNL is expected to always have a uniform distribution
+	 * of EU across subslices with the exception that any one
+	 * EU in any one subslice may be fused off for die
+	 * recovery.
+	 */
+	sseu->eu_per_subslice = sseu_subslice_total(sseu) ?
+				DIV_ROUND_UP(sseu->eu_total,
+					     sseu_subslice_total(sseu)) : 0;
+
+	/* No restrictions on Power Gating */
+	sseu->has_slice_pg = 1;
+	sseu->has_subslice_pg = 1;
+	sseu->has_eu_pg = 1;
+}
+
 static void cherryview_sseu_info_init(struct drm_i915_private *dev_priv)
 {
 	struct sseu_dev_info *sseu = &mkwrite_device_info(dev_priv)->sseu;
@@ -409,8 +442,10 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
 		cherryview_sseu_info_init(dev_priv);
 	else if (IS_BROADWELL(dev_priv))
 		broadwell_sseu_info_init(dev_priv);
-	else if (INTEL_INFO(dev_priv)->gen >= 9)
+	else if (INTEL_GEN(dev_priv) == 9)
 		gen9_sseu_info_init(dev_priv);
+	else if (INTEL_GEN(dev_priv) >= 10)
+		gen10_sseu_info_init(dev_priv);
 
 	DRM_DEBUG_DRIVER("slice mask: %04x\n", info->sseu.slice_mask);
 	DRM_DEBUG_DRIVER("slice total: %u\n", hweight8(info->sseu.slice_mask));
-- 
2.13.5

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[PATCH 2/2] drm/i915/cnl: Fix SSEU Device Status.

[Rodrigo Vivi]

CNL adds an extra register for slice/subslice information.
Although no SKU is planed with an extra slice let's already
handle this extra piece of information so we don't have the
risk in future of getting a part that might have chosen this
part of the die instead of other slices or anything like that.

Also if subslice is disabled the information of eu ack for that
is garbage, so let's skip checks for eu if subslice is disabled
as we skip the subslice if slice is disabled.

The rest is pretty much like gen9.

v2: Remove IS_CANNONLAKE from gen9 status function.

Cc: Oscar Mateo <oscar.mateo@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Oscar Mateo <oscar.mateo@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 54 +++++++++++++++++++++++++++++++++++--
 drivers/gpu/drm/i915/i915_reg.h     |  6 +++++
 2 files changed, 58 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index ca6fa6d122c6..e86d2be4b815 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -4575,6 +4575,54 @@ static void cherryview_sseu_device_status(struct drm_i915_private *dev_priv,
 	}
 }
 
+static void gen10_sseu_device_status(struct drm_i915_private *dev_priv,
+				     struct sseu_dev_info *sseu)
+{
+	const struct intel_device_info *info = INTEL_INFO(dev_priv);
+	int s_max = 4, ss_max = 3;
+	int s, ss;
+	u32 s_reg[s_max], eu_reg[2 * s_max], eu_mask[2];
+
+	for (s = 0; s < s_max; s++) {
+		s_reg[s] = I915_READ(GEN10_SLICE_PGCTL_ACK(s));
+		eu_reg[2 * s] = I915_READ(GEN10_SS01_EU_PGCTL_ACK(s));
+		eu_reg[2 * s + 1] = I915_READ(GEN10_SS23_EU_PGCTL_ACK(s));
+	}
+
+	eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
+		     GEN9_PGCTL_SSA_EU19_ACK |
+		     GEN9_PGCTL_SSA_EU210_ACK |
+		     GEN9_PGCTL_SSA_EU311_ACK;
+	eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
+		     GEN9_PGCTL_SSB_EU19_ACK |
+		     GEN9_PGCTL_SSB_EU210_ACK |
+		     GEN9_PGCTL_SSB_EU311_ACK;
+
+	for (s = 0; s < s_max; s++) {
+		if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
+			/* skip disabled slice */
+			continue;
+
+		sseu->slice_mask |= BIT(s);
+		sseu->subslice_mask = info->sseu.subslice_mask;
+
+		for (ss = 0; ss < ss_max; ss++) {
+			unsigned int eu_cnt;
+
+			if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
+				/* skip disabled subslice */
+				continue;
+
+			eu_cnt = 2 * hweight32(eu_reg[2 * s + ss / 2] &
+					       eu_mask[ss % 2]);
+			sseu->eu_total += eu_cnt;
+			sseu->eu_per_subslice = max_t(unsigned int,
+						      sseu->eu_per_subslice,
+						      eu_cnt);
+		}
+	}
+}
+
 static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
 				    struct sseu_dev_info *sseu)
 {
@@ -4610,7 +4658,7 @@ static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
 
 		sseu->slice_mask |= BIT(s);
 
-		if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv))
+		if (IS_GEN9_BC(dev_priv))
 			sseu->subslice_mask =
 				INTEL_INFO(dev_priv)->sseu.subslice_mask;
 
@@ -4716,8 +4764,10 @@ static int i915_sseu_status(struct seq_file *m, void *unused)
 		cherryview_sseu_device_status(dev_priv, &sseu);
 	} else if (IS_BROADWELL(dev_priv)) {
 		broadwell_sseu_device_status(dev_priv, &sseu);
-	} else if (INTEL_GEN(dev_priv) >= 9) {
+	} else if (IS_GEN9(dev_priv)) {
 		gen9_sseu_device_status(dev_priv, &sseu);
+	} else if (INTEL_GEN(dev_priv) >= 10) {
+		gen10_sseu_device_status(dev_priv, &sseu);
 	}
 
 	intel_runtime_pm_put(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9f4b8faf2982..93b688666419 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8018,11 +8018,17 @@ enum {
 #define   CHV_EU311_PG_ENABLE		(1<<1)
 
 #define GEN9_SLICE_PGCTL_ACK(slice)	_MMIO(0x804c + (slice)*0x4)
+#define GEN10_SLICE_PGCTL_ACK(slice)	((slice) == 3 ? _MMIO(0x8080) : \
+					 GEN9_SLICE_PGCTL_ACK((slice)))
 #define   GEN9_PGCTL_SLICE_ACK		(1 << 0)
 #define   GEN9_PGCTL_SS_ACK(subslice)	(1 << (2 + (subslice)*2))
 
 #define GEN9_SS01_EU_PGCTL_ACK(slice)	_MMIO(0x805c + (slice)*0x8)
+#define GEN10_SS01_EU_PGCTL_ACK(slice)	((slice) == 3 ? _MMIO(0x808c) : \
+					 GEN9_SS01_EU_PGCTL_ACK((slice)))
 #define GEN9_SS23_EU_PGCTL_ACK(slice)	_MMIO(0x8060 + (slice)*0x8)
+#define GEN10_SS23_EU_PGCTL_ACK(slice)	((slice) == 3 ? _MMIO(0x8090) : \
+					 GEN9_SS23_EU_PGCTL_ACK((slice)))
 #define   GEN9_PGCTL_SSA_EU08_ACK	(1 << 0)
 #define   GEN9_PGCTL_SSA_EU19_ACK	(1 << 2)
 #define   GEN9_PGCTL_SSA_EU210_ACK	(1 << 4)
-- 
2.13.5

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Re: [PATCH 2/2] drm/i915/cnl: Fix SSEU Device Status.

[Oscar Mateo]

On 09/19/2017 03:06 PM, Rodrigo Vivi wrote:
> CNL adds an extra register for slice/subslice information.
> Although no SKU is planed with an extra slice let's already
> handle this extra piece of information so we don't have the
> risk in future of getting a part that might have chosen this
> part of the die instead of other slices or anything like that.
>
> Also if subslice is disabled the information of eu ack for that
> is garbage, so let's skip checks for eu if subslice is disabled
> as we skip the subslice if slice is disabled.
>
> The rest is pretty much like gen9.
>
> v2: Remove IS_CANNONLAKE from gen9 status function.
>
> Cc: Oscar Mateo <oscar.mateo@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Reviewed-by: Oscar Mateo <oscar.mateo@intel.com>
> ---
>   drivers/gpu/drm/i915/i915_debugfs.c | 54 +++++++++++++++++++++++++++++++++++--
>   drivers/gpu/drm/i915/i915_reg.h     |  6 +++++
>   2 files changed, 58 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index ca6fa6d122c6..e86d2be4b815 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -4575,6 +4575,54 @@ static void cherryview_sseu_device_status(struct drm_i915_private *dev_priv,
>   	}
>   }
>   
> +static void gen10_sseu_device_status(struct drm_i915_private *dev_priv,
> +				     struct sseu_dev_info *sseu)
> +{
> +	const struct intel_device_info *info = INTEL_INFO(dev_priv);
> +	int s_max = 4, ss_max = 3;

Now the two patches are misaligned in the sense that the other one 
considers s_max = 6 and ss_max = 4
It's not very important because this is only debugfs and we know from 
the specs that s_max = 4 and ss_max = 3 are enough to cover all 
real-life scenarios, but can we explain this in a comment before merging?
Thanks!

> +	int s, ss;
> +	u32 s_reg[s_max], eu_reg[2 * s_max], eu_mask[2];
> +
> +	for (s = 0; s < s_max; s++) {
> +		s_reg[s] = I915_READ(GEN10_SLICE_PGCTL_ACK(s));
> +		eu_reg[2 * s] = I915_READ(GEN10_SS01_EU_PGCTL_ACK(s));
> +		eu_reg[2 * s + 1] = I915_READ(GEN10_SS23_EU_PGCTL_ACK(s));
> +	}
> +
> +	eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
> +		     GEN9_PGCTL_SSA_EU19_ACK |
> +		     GEN9_PGCTL_SSA_EU210_ACK |
> +		     GEN9_PGCTL_SSA_EU311_ACK;
> +	eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
> +		     GEN9_PGCTL_SSB_EU19_ACK |
> +		     GEN9_PGCTL_SSB_EU210_ACK |
> +		     GEN9_PGCTL_SSB_EU311_ACK;
> +
> +	for (s = 0; s < s_max; s++) {
> +		if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
> +			/* skip disabled slice */
> +			continue;
> +
> +		sseu->slice_mask |= BIT(s);
> +		sseu->subslice_mask = info->sseu.subslice_mask;
> +
> +		for (ss = 0; ss < ss_max; ss++) {
> +			unsigned int eu_cnt;
> +
> +			if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
> +				/* skip disabled subslice */
> +				continue;
> +
> +			eu_cnt = 2 * hweight32(eu_reg[2 * s + ss / 2] &
> +					       eu_mask[ss % 2]);
> +			sseu->eu_total += eu_cnt;
> +			sseu->eu_per_subslice = max_t(unsigned int,
> +						      sseu->eu_per_subslice,
> +						      eu_cnt);
> +		}
> +	}
> +}
> +
>   static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
>   				    struct sseu_dev_info *sseu)
>   {
> @@ -4610,7 +4658,7 @@ static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
>   
>   		sseu->slice_mask |= BIT(s);
>   
> -		if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv))
> +		if (IS_GEN9_BC(dev_priv))
>   			sseu->subslice_mask =
>   				INTEL_INFO(dev_priv)->sseu.subslice_mask;
>   
> @@ -4716,8 +4764,10 @@ static int i915_sseu_status(struct seq_file *m, void *unused)
>   		cherryview_sseu_device_status(dev_priv, &sseu);
>   	} else if (IS_BROADWELL(dev_priv)) {
>   		broadwell_sseu_device_status(dev_priv, &sseu);
> -	} else if (INTEL_GEN(dev_priv) >= 9) {
> +	} else if (IS_GEN9(dev_priv)) {
>   		gen9_sseu_device_status(dev_priv, &sseu);
> +	} else if (INTEL_GEN(dev_priv) >= 10) {
> +		gen10_sseu_device_status(dev_priv, &sseu);
>   	}
>   
>   	intel_runtime_pm_put(dev_priv);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 9f4b8faf2982..93b688666419 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8018,11 +8018,17 @@ enum {
>   #define   CHV_EU311_PG_ENABLE		(1<<1)
>   
>   #define GEN9_SLICE_PGCTL_ACK(slice)	_MMIO(0x804c + (slice)*0x4)
> +#define GEN10_SLICE_PGCTL_ACK(slice)	((slice) == 3 ? _MMIO(0x8080) : \
> +					 GEN9_SLICE_PGCTL_ACK((slice)))
>   #define   GEN9_PGCTL_SLICE_ACK		(1 << 0)
>   #define   GEN9_PGCTL_SS_ACK(subslice)	(1 << (2 + (subslice)*2))
>   
>   #define GEN9_SS01_EU_PGCTL_ACK(slice)	_MMIO(0x805c + (slice)*0x8)
> +#define GEN10_SS01_EU_PGCTL_ACK(slice)	((slice) == 3 ? _MMIO(0x808c) : \
> +					 GEN9_SS01_EU_PGCTL_ACK((slice)))
>   #define GEN9_SS23_EU_PGCTL_ACK(slice)	_MMIO(0x8060 + (slice)*0x8)
> +#define GEN10_SS23_EU_PGCTL_ACK(slice)	((slice) == 3 ? _MMIO(0x8090) : \
> +					 GEN9_SS23_EU_PGCTL_ACK((slice)))
>   #define   GEN9_PGCTL_SSA_EU08_ACK	(1 << 0)
>   #define   GEN9_PGCTL_SSA_EU19_ACK	(1 << 2)
>   #define   GEN9_PGCTL_SSA_EU210_ACK	(1 << 4)

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✗ Fi.CI.BAT: warning for series starting with [1/2] drm/i915/cnl: Add support slice/subslice/eu configs

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915/cnl: Add support slice/subslice/eu configs
URL   : https://patchwork.freedesktop.org/series/30629/
State : warning

== Summary ==

Series 30629v1 series starting with [1/2] drm/i915/cnl: Add support slice/subslice/eu configs
https://patchwork.freedesktop.org/api/1.0/series/30629/revisions/1/mbox/

Test gem_exec_reloc:
        Subgroup basic-write-read-noreloc:
                pass       -> DMESG-WARN (fi-kbl-7500u)
Test gem_exec_store:
        Subgroup basic-vebox:
                pass       -> DMESG-WARN (fi-kbl-7500u)
Test gem_exec_suspend:
        Subgroup basic-s3:
                pass       -> INCOMPLETE (fi-kbl-7500u) fdo#102850
Test kms_cursor_legacy:
        Subgroup basic-busy-flip-before-cursor-legacy:
                pass       -> FAIL       (fi-snb-2600) fdo#100215
Test kms_pipe_crc_basic:
        Subgroup hang-read-crc-pipe-b:
                incomplete -> DMESG-WARN (fi-cfl-s) fdo#102294
Test drv_module_reload:
        Subgroup basic-reload:
                pass       -> DMESG-WARN (fi-glk-1) fdo#102777

fdo#102850 https://bugs.freedesktop.org/show_bug.cgi?id=102850
fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215
fdo#102294 https://bugs.freedesktop.org/show_bug.cgi?id=102294
fdo#102777 https://bugs.freedesktop.org/show_bug.cgi?id=102777

fi-bdw-5557u     total:289  pass:268  dwarn:0   dfail:0   fail:0   skip:21  time:444s
fi-bdw-gvtdvm    total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  time:463s
fi-blb-e6850     total:289  pass:224  dwarn:1   dfail:0   fail:0   skip:64  time:418s
fi-bsw-n3050     total:289  pass:243  dwarn:0   dfail:0   fail:0   skip:46  time:509s
fi-bwr-2160      total:289  pass:184  dwarn:0   dfail:0   fail:0   skip:105 time:278s
fi-bxt-j4205     total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  time:498s
fi-byt-j1900     total:289  pass:254  dwarn:1   dfail:0   fail:0   skip:34  time:489s
fi-byt-n2820     total:289  pass:250  dwarn:1   dfail:0   fail:0   skip:38  time:501s
fi-cfl-s         total:289  pass:222  dwarn:35  dfail:0   fail:0   skip:32  time:548s
fi-elk-e7500     total:289  pass:230  dwarn:0   dfail:0   fail:0   skip:59  time:413s
fi-glk-1         total:289  pass:259  dwarn:1   dfail:0   fail:0   skip:29  time:563s
fi-hsw-4770      total:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  time:423s
fi-hsw-4770r     total:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  time:408s
fi-ilk-650       total:289  pass:229  dwarn:0   dfail:0   fail:0   skip:60  time:426s
fi-ivb-3520m     total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  time:480s
fi-ivb-3770      total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  time:459s
fi-kbl-7500u     total:118  pass:98   dwarn:3   dfail:0   fail:0   skip:16 
fi-kbl-7560u     total:289  pass:270  dwarn:0   dfail:0   fail:0   skip:19  time:575s
fi-kbl-r         total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  time:588s
fi-pnv-d510      total:289  pass:223  dwarn:1   dfail:0   fail:0   skip:65  time:549s
fi-skl-6260u     total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  time:450s
fi-skl-6700k     total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  time:751s
fi-skl-6770hq    total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  time:488s
fi-skl-gvtdvm    total:289  pass:266  dwarn:0   dfail:0   fail:0   skip:23  time:466s
fi-snb-2520m     total:289  pass:251  dwarn:0   dfail:0   fail:0   skip:38  time:564s
fi-snb-2600      total:289  pass:249  dwarn:0   dfail:0   fail:1   skip:39  time:417s

bf6ecf6d25c1c45e576643b7d7a65e8b1e6b4f01 drm-tip: 2017y-09m-19d-17h-23m-04s UTC integration manifest
9818047933cf drm/i915/cnl: Fix SSEU Device Status.
2927b87c3d3d drm/i915/cnl: Add support slice/subslice/eu configs

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5760/
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Re: [PATCH 1/2] drm/i915/cnl: Add support slice/subslice/eu configs

[Oscar Mateo]

On 09/19/2017 03:06 PM, Rodrigo Vivi wrote:
> From: Ben Widawsky <ben@bwidawsk.net>
>
> Cannonlake Slice and Subslice information has changed.
>
> This patch initially provided by Ben adds the proper sseu
> initialization.
>
> v2: This v2 done by Rodrigo includes:
>      - Fix on Total slices count by avoiding [1][2] and [2][2].
>      - Inclusion of EU Per Subslice.
>      - Commit message.
> v3: This v3 done by Rodrigo includes:
>      - Handle all possible bits and extra fuse register.
>      - Use INTEL_GEN macro.
>      - Fully assume uniform distribution so remove union
>        with eu_per_subslice and add proper the comment.
> v4: This v4 done by Rodrigo includes:
>      - Consider all bits available: 6 bits for slices [27:22]
>        and 4 for subslices [21:18].
> v5: This v5 done by Rodrigo includes:
>      - sseu->subslice_mask = (1 << 4) - 1 - missed on previous
>      versions and noticed by Oscar.
>
> Cc: Oscar Mateo <oscar.mateo@intel.com>
> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
>   drivers/gpu/drm/i915/i915_reg.h          |  8 +++++++
>   drivers/gpu/drm/i915/intel_device_info.c | 37 +++++++++++++++++++++++++++++++-
>   2 files changed, 44 insertions(+), 1 deletion(-)

Reviewed-by: Oscar Mateo <oscar.mateo@intel.com>

> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 94b40a469afd..9f4b8faf2982 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2730,6 +2730,11 @@ enum i915_power_well_id {
>   #define   GEN9_F2_SS_DIS_SHIFT		20
>   #define   GEN9_F2_SS_DIS_MASK		(0xf << GEN9_F2_SS_DIS_SHIFT)
>   
> +#define   GEN10_F2_S_ENA_SHIFT		22
> +#define   GEN10_F2_S_ENA_MASK		(0x3f << GEN10_F2_S_ENA_SHIFT)
> +#define   GEN10_F2_SS_DIS_SHIFT		18
> +#define   GEN10_F2_SS_DIS_MASK		(0xf << GEN10_F2_SS_DIS_SHIFT)
> +
>   #define GEN8_EU_DISABLE0		_MMIO(0x9134)
>   #define   GEN8_EU_DIS0_S0_MASK		0xffffff
>   #define   GEN8_EU_DIS0_S1_SHIFT		24
> @@ -2745,6 +2750,9 @@ enum i915_power_well_id {
>   
>   #define GEN9_EU_DISABLE(slice)		_MMIO(0x9134 + (slice)*0x4)
>   
> +#define GEN10_EU_DISABLE3		_MMIO(0x9140)
> +#define   GEN10_EU_DIS_SS_MASK		0xff
> +
>   #define GEN6_BSD_SLEEP_PSMI_CONTROL	_MMIO(0x12050)
>   #define   GEN6_BSD_SLEEP_MSG_DISABLE	(1 << 0)
>   #define   GEN6_BSD_SLEEP_FLUSH_DISABLE	(1 << 2)
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index 43831b09b47a..d2e7ae61775d 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -82,6 +82,39 @@ void intel_device_info_dump(struct drm_i915_private *dev_priv)
>   #undef PRINT_FLAG
>   }
>   
> +static void gen10_sseu_info_init(struct drm_i915_private *dev_priv)
> +{
> +	struct sseu_dev_info *sseu = &mkwrite_device_info(dev_priv)->sseu;
> +	const u32 fuse2 = I915_READ(GEN8_FUSE2);
> +
> +	sseu->slice_mask = (fuse2 & GEN10_F2_S_ENA_MASK) >>
> +			    GEN10_F2_S_ENA_SHIFT;
> +	sseu->subslice_mask = (1 << 4) - 1;
> +	sseu->subslice_mask &= ~((fuse2 & GEN10_F2_SS_DIS_MASK) >>
> +				 GEN10_F2_SS_DIS_SHIFT);
> +
> +	sseu->eu_total = hweight32(~I915_READ(GEN8_EU_DISABLE0));
> +	sseu->eu_total += hweight32(~I915_READ(GEN8_EU_DISABLE1));
> +	sseu->eu_total += hweight32(~I915_READ(GEN8_EU_DISABLE2));
> +	sseu->eu_total += hweight8(~(I915_READ(GEN10_EU_DISABLE3) &
> +				     GEN10_EU_DIS_SS_MASK));
> +
> +	/*
> +	 * CNL is expected to always have a uniform distribution
> +	 * of EU across subslices with the exception that any one
> +	 * EU in any one subslice may be fused off for die
> +	 * recovery.
> +	 */
> +	sseu->eu_per_subslice = sseu_subslice_total(sseu) ?
> +				DIV_ROUND_UP(sseu->eu_total,
> +					     sseu_subslice_total(sseu)) : 0;
> +
> +	/* No restrictions on Power Gating */
> +	sseu->has_slice_pg = 1;
> +	sseu->has_subslice_pg = 1;
> +	sseu->has_eu_pg = 1;
> +}
> +
>   static void cherryview_sseu_info_init(struct drm_i915_private *dev_priv)
>   {
>   	struct sseu_dev_info *sseu = &mkwrite_device_info(dev_priv)->sseu;
> @@ -409,8 +442,10 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
>   		cherryview_sseu_info_init(dev_priv);
>   	else if (IS_BROADWELL(dev_priv))
>   		broadwell_sseu_info_init(dev_priv);
> -	else if (INTEL_INFO(dev_priv)->gen >= 9)
> +	else if (INTEL_GEN(dev_priv) == 9)
>   		gen9_sseu_info_init(dev_priv);
> +	else if (INTEL_GEN(dev_priv) >= 10)
> +		gen10_sseu_info_init(dev_priv);
>   
>   	DRM_DEBUG_DRIVER("slice mask: %04x\n", info->sseu.slice_mask);
>   	DRM_DEBUG_DRIVER("slice total: %u\n", hweight8(info->sseu.slice_mask));

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[PATCH 1/2] drm/i915/cnl: Add support slice/subslice/eu configs

[Rodrigo Vivi]

From: Ben Widawsky <ben@bwidawsk.net>

Cannonlake Slice and Subslice information has changed.

This patch initially provided by Ben adds the proper sseu
initialization.

v2: This v2 done by Rodrigo includes:
    - Fix on Total slices count by avoiding [1][2] and [2][2].
    - Inclusion of EU Per Subslice.
    - Commit message.
v3: This v3 done by Rodrigo includes:
    - Handle all possible bits and extra fuse register.
    - Use INTEL_GEN macro.
    - Fully assume uniform distribution so remove union
      with eu_per_subslice and add proper the comment.
v4: This v4 done by Rodrigo includes:
    - Consider all bits available: 6 bits for slices [27:22]
      and 4 for subslices [21:18].
v5: This v5 done by Rodrigo includes:
    - sseu->subslice_mask = (1 << 4) - 1 - missed on previous
    versions and noticed by Oscar.

Cc: Oscar Mateo <oscar.mateo@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Oscar Mateo <oscar.mateo@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h          |  8 +++++++
 drivers/gpu/drm/i915/intel_device_info.c | 37 +++++++++++++++++++++++++++++++-
 2 files changed, 44 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 82f36dd0cd94..1c257797c583 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2730,6 +2730,11 @@ enum i915_power_well_id {
 #define   GEN9_F2_SS_DIS_SHIFT		20
 #define   GEN9_F2_SS_DIS_MASK		(0xf << GEN9_F2_SS_DIS_SHIFT)
 
+#define   GEN10_F2_S_ENA_SHIFT		22
+#define   GEN10_F2_S_ENA_MASK		(0x3f << GEN10_F2_S_ENA_SHIFT)
+#define   GEN10_F2_SS_DIS_SHIFT		18
+#define   GEN10_F2_SS_DIS_MASK		(0xf << GEN10_F2_SS_DIS_SHIFT)
+
 #define GEN8_EU_DISABLE0		_MMIO(0x9134)
 #define   GEN8_EU_DIS0_S0_MASK		0xffffff
 #define   GEN8_EU_DIS0_S1_SHIFT		24
@@ -2745,6 +2750,9 @@ enum i915_power_well_id {
 
 #define GEN9_EU_DISABLE(slice)		_MMIO(0x9134 + (slice)*0x4)
 
+#define GEN10_EU_DISABLE3		_MMIO(0x9140)
+#define   GEN10_EU_DIS_SS_MASK		0xff
+
 #define GEN6_BSD_SLEEP_PSMI_CONTROL	_MMIO(0x12050)
 #define   GEN6_BSD_SLEEP_MSG_DISABLE	(1 << 0)
 #define   GEN6_BSD_SLEEP_FLUSH_DISABLE	(1 << 2)
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 43831b09b47a..d2e7ae61775d 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -82,6 +82,39 @@ void intel_device_info_dump(struct drm_i915_private *dev_priv)
 #undef PRINT_FLAG
 }
 
+static void gen10_sseu_info_init(struct drm_i915_private *dev_priv)
+{
+	struct sseu_dev_info *sseu = &mkwrite_device_info(dev_priv)->sseu;
+	const u32 fuse2 = I915_READ(GEN8_FUSE2);
+
+	sseu->slice_mask = (fuse2 & GEN10_F2_S_ENA_MASK) >>
+			    GEN10_F2_S_ENA_SHIFT;
+	sseu->subslice_mask = (1 << 4) - 1;
+	sseu->subslice_mask &= ~((fuse2 & GEN10_F2_SS_DIS_MASK) >>
+				 GEN10_F2_SS_DIS_SHIFT);
+
+	sseu->eu_total = hweight32(~I915_READ(GEN8_EU_DISABLE0));
+	sseu->eu_total += hweight32(~I915_READ(GEN8_EU_DISABLE1));
+	sseu->eu_total += hweight32(~I915_READ(GEN8_EU_DISABLE2));
+	sseu->eu_total += hweight8(~(I915_READ(GEN10_EU_DISABLE3) &
+				     GEN10_EU_DIS_SS_MASK));
+
+	/*
+	 * CNL is expected to always have a uniform distribution
+	 * of EU across subslices with the exception that any one
+	 * EU in any one subslice may be fused off for die
+	 * recovery.
+	 */
+	sseu->eu_per_subslice = sseu_subslice_total(sseu) ?
+				DIV_ROUND_UP(sseu->eu_total,
+					     sseu_subslice_total(sseu)) : 0;
+
+	/* No restrictions on Power Gating */
+	sseu->has_slice_pg = 1;
+	sseu->has_subslice_pg = 1;
+	sseu->has_eu_pg = 1;
+}
+
 static void cherryview_sseu_info_init(struct drm_i915_private *dev_priv)
 {
 	struct sseu_dev_info *sseu = &mkwrite_device_info(dev_priv)->sseu;
@@ -409,8 +442,10 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
 		cherryview_sseu_info_init(dev_priv);
 	else if (IS_BROADWELL(dev_priv))
 		broadwell_sseu_info_init(dev_priv);
-	else if (INTEL_INFO(dev_priv)->gen >= 9)
+	else if (INTEL_GEN(dev_priv) == 9)
 		gen9_sseu_info_init(dev_priv);
+	else if (INTEL_GEN(dev_priv) >= 10)
+		gen10_sseu_info_init(dev_priv);
 
 	DRM_DEBUG_DRIVER("slice mask: %04x\n", info->sseu.slice_mask);
 	DRM_DEBUG_DRIVER("slice total: %u\n", hweight8(info->sseu.slice_mask));
-- 
2.13.5

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[PATCH 1/2] drm/i915/cnl: Add support slice/subslice/eu configs

[Rodrigo Vivi]

From: Ben Widawsky <ben@bwidawsk.net>

Cannonlake Slice and Subslice information has changed.

This patch initially provided by Ben adds the proper sseu
initialization.

v2: This v2 done by Rodrigo includes:
    - Fix on Total slices count by avoiding [1][2] and [2][2].
    - Inclusion of EU Per Subslice.
    - Commit message.
v3: This v3 done by Rodrigo includes:
    - Handle all possible bits and extra fuse register.
    - Use INTEL_GEN macro.
    - Fully assume uniform distribution so remove union
      with eu_per_subslice and add proper the comment.

Cc: Oscar Mateo <oscar.mateo@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h          |  8 +++++++
 drivers/gpu/drm/i915/intel_device_info.c | 37 +++++++++++++++++++++++++++++++-
 2 files changed, 44 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 94b40a469afd..4db5deddfb9f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2730,6 +2730,11 @@ enum i915_power_well_id {
 #define   GEN9_F2_SS_DIS_SHIFT		20
 #define   GEN9_F2_SS_DIS_MASK		(0xf << GEN9_F2_SS_DIS_SHIFT)
 
+#define   GEN10_F2_S_ENA_SHIFT		22
+#define   GEN10_F2_S_ENA_MASK		(0xf << GEN10_F2_S_ENA_SHIFT)
+#define   GEN10_F2_SS_DIS_SHIFT		18
+#define   GEN10_F2_SS_DIS_MASK		(0x7 << GEN10_F2_SS_DIS_SHIFT)
+
 #define GEN8_EU_DISABLE0		_MMIO(0x9134)
 #define   GEN8_EU_DIS0_S0_MASK		0xffffff
 #define   GEN8_EU_DIS0_S1_SHIFT		24
@@ -2745,6 +2750,9 @@ enum i915_power_well_id {
 
 #define GEN9_EU_DISABLE(slice)		_MMIO(0x9134 + (slice)*0x4)
 
+#define GEN10_EU_DISABLE3		_MMIO(0x9140)
+#define   GEN10_EU_DIS_SS_MASK		0xff
+
 #define GEN6_BSD_SLEEP_PSMI_CONTROL	_MMIO(0x12050)
 #define   GEN6_BSD_SLEEP_MSG_DISABLE	(1 << 0)
 #define   GEN6_BSD_SLEEP_FLUSH_DISABLE	(1 << 2)
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 43831b09b47a..85693811c1b0 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -82,6 +82,39 @@ void intel_device_info_dump(struct drm_i915_private *dev_priv)
 #undef PRINT_FLAG
 }
 
+static void gen10_sseu_info_init(struct drm_i915_private *dev_priv)
+{
+	struct sseu_dev_info *sseu = &mkwrite_device_info(dev_priv)->sseu;
+	const u32 fuse2 = I915_READ(GEN8_FUSE2);
+
+	sseu->slice_mask = (fuse2 & GEN10_F2_S_ENA_MASK) >>
+			    GEN10_F2_S_ENA_SHIFT;
+	sseu->subslice_mask = (1 << 3) - 1;
+	sseu->subslice_mask &= ~((fuse2 & GEN10_F2_SS_DIS_MASK) >>
+				 GEN10_F2_SS_DIS_SHIFT);
+
+	sseu->eu_total = hweight32(~I915_READ(GEN8_EU_DISABLE0));
+	sseu->eu_total += hweight32(~I915_READ(GEN8_EU_DISABLE1));
+	sseu->eu_total += hweight32(~I915_READ(GEN8_EU_DISABLE2));
+	sseu->eu_total += hweight8(~(I915_READ(GEN10_EU_DISABLE3) &
+				     GEN10_EU_DIS_SS_MASK));
+
+	/*
+	 * CNL is expected to always have a uniform distribution
+	 * of EU across subslices with the exception that any one
+	 * EU in any one subslice may be fused off for die
+	 * recovery.
+	 */
+	sseu->eu_per_subslice = sseu_subslice_total(sseu) ?
+				DIV_ROUND_UP(sseu->eu_total,
+					     sseu_subslice_total(sseu)) : 0;
+
+	/* No restrictions on Power Gating */
+	sseu->has_slice_pg = 1;
+	sseu->has_subslice_pg = 1;
+	sseu->has_eu_pg = 1;
+}
+
 static void cherryview_sseu_info_init(struct drm_i915_private *dev_priv)
 {
 	struct sseu_dev_info *sseu = &mkwrite_device_info(dev_priv)->sseu;
@@ -409,8 +442,10 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
 		cherryview_sseu_info_init(dev_priv);
 	else if (IS_BROADWELL(dev_priv))
 		broadwell_sseu_info_init(dev_priv);
-	else if (INTEL_INFO(dev_priv)->gen >= 9)
+	else if (INTEL_GEN(dev_priv) == 9)
 		gen9_sseu_info_init(dev_priv);
+	else if (INTEL_GEN(dev_priv) >= 10)
+		gen10_sseu_info_init(dev_priv);
 
 	DRM_DEBUG_DRIVER("slice mask: %04x\n", info->sseu.slice_mask);
 	DRM_DEBUG_DRIVER("slice total: %u\n", hweight8(info->sseu.slice_mask));
-- 
2.13.5

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Re: [PATCH 1/2] drm/i915/cnl: Add support slice/subslice/eu configs

[Oscar Mateo]

On 09/18/2017 11:49 AM, Rodrigo Vivi wrote:
> From: Ben Widawsky <ben@bwidawsk.net>
>
> Cannonlake Slice and Subslice information has changed.
>
> This patch initially provided by Ben adds the proper sseu
> initialization.
>
> v2: This v2 done by Rodrigo includes:
>      - Fix on Total slices count by avoiding [1][2] and [2][2].
>      - Inclusion of EU Per Subslice.
>      - Commit message.
> v3: This v3 done by Rodrigo includes:
>      - Handle all possible bits and extra fuse register.
>      - Use INTEL_GEN macro.
>      - Fully assume uniform distribution so remove union
>        with eu_per_subslice and add proper the comment.
>
> Cc: Oscar Mateo <oscar.mateo@intel.com>
> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
>   drivers/gpu/drm/i915/i915_reg.h          |  8 +++++++
>   drivers/gpu/drm/i915/intel_device_info.c | 37 +++++++++++++++++++++++++++++++-
>   2 files changed, 44 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 94b40a469afd..4db5deddfb9f 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2730,6 +2730,11 @@ enum i915_power_well_id {
>   #define   GEN9_F2_SS_DIS_SHIFT		20
>   #define   GEN9_F2_SS_DIS_MASK		(0xf << GEN9_F2_SS_DIS_SHIFT)
>   
> +#define   GEN10_F2_S_ENA_SHIFT		22
> +#define   GEN10_F2_S_ENA_MASK		(0xf << GEN10_F2_S_ENA_SHIFT)
> +#define   GEN10_F2_SS_DIS_SHIFT		18
> +#define   GEN10_F2_SS_DIS_MASK		(0x7 << GEN10_F2_SS_DIS_SHIFT)
> +
>   #define GEN8_EU_DISABLE0		_MMIO(0x9134)
>   #define   GEN8_EU_DIS0_S0_MASK		0xffffff
>   #define   GEN8_EU_DIS0_S1_SHIFT		24
> @@ -2745,6 +2750,9 @@ enum i915_power_well_id {
>   
>   #define GEN9_EU_DISABLE(slice)		_MMIO(0x9134 + (slice)*0x4)
>   
> +#define GEN10_EU_DISABLE3		_MMIO(0x9140)
> +#define   GEN10_EU_DIS_SS_MASK		0xff
> +
>   #define GEN6_BSD_SLEEP_PSMI_CONTROL	_MMIO(0x12050)
>   #define   GEN6_BSD_SLEEP_MSG_DISABLE	(1 << 0)
>   #define   GEN6_BSD_SLEEP_FLUSH_DISABLE	(1 << 2)
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index 43831b09b47a..85693811c1b0 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -82,6 +82,39 @@ void intel_device_info_dump(struct drm_i915_private *dev_priv)
>   #undef PRINT_FLAG
>   }
>   
> +static void gen10_sseu_info_init(struct drm_i915_private *dev_priv)
> +{
> +	struct sseu_dev_info *sseu = &mkwrite_device_info(dev_priv)->sseu;
> +	const u32 fuse2 = I915_READ(GEN8_FUSE2);
> +
> +	sseu->slice_mask = (fuse2 & GEN10_F2_S_ENA_MASK) >>
> +			    GEN10_F2_S_ENA_SHIFT;
> +	sseu->subslice_mask = (1 << 3) - 1;
> +	sseu->subslice_mask &= ~((fuse2 & GEN10_F2_SS_DIS_MASK) >>
> +				 GEN10_F2_SS_DIS_SHIFT);
> +
> +	sseu->eu_total = hweight32(~I915_READ(GEN8_EU_DISABLE0));
> +	sseu->eu_total += hweight32(~I915_READ(GEN8_EU_DISABLE1));
> +	sseu->eu_total += hweight32(~I915_READ(GEN8_EU_DISABLE2));
> +	sseu->eu_total += hweight8(~(I915_READ(GEN10_EU_DISABLE3) &
> +				     GEN10_EU_DIS_SS_MASK));

This looks better than before, but since we are only reading 4 bits for 
the slice mask (GEN10_F2_S_ENA_MASK = 0xf), why do we bother with slices 
4 and 5 for the EU count?

> +	/*
> +	 * CNL is expected to always have a uniform distribution
> +	 * of EU across subslices with the exception that any one
> +	 * EU in any one subslice may be fused off for die
> +	 * recovery.
> +	 */
> +	sseu->eu_per_subslice = sseu_subslice_total(sseu) ?
> +				DIV_ROUND_UP(sseu->eu_total,
> +					     sseu_subslice_total(sseu)) : 0;
> +
> +	/* No restrictions on Power Gating */
> +	sseu->has_slice_pg = 1;
> +	sseu->has_subslice_pg = 1;
> +	sseu->has_eu_pg = 1;
> +}
> +
>   static void cherryview_sseu_info_init(struct drm_i915_private *dev_priv)
>   {
>   	struct sseu_dev_info *sseu = &mkwrite_device_info(dev_priv)->sseu;
> @@ -409,8 +442,10 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
>   		cherryview_sseu_info_init(dev_priv);
>   	else if (IS_BROADWELL(dev_priv))
>   		broadwell_sseu_info_init(dev_priv);
> -	else if (INTEL_INFO(dev_priv)->gen >= 9)
> +	else if (INTEL_GEN(dev_priv) == 9)
>   		gen9_sseu_info_init(dev_priv);
> +	else if (INTEL_GEN(dev_priv) >= 10)
> +		gen10_sseu_info_init(dev_priv);
>   
>   	DRM_DEBUG_DRIVER("slice mask: %04x\n", info->sseu.slice_mask);
>   	DRM_DEBUG_DRIVER("slice total: %u\n", hweight8(info->sseu.slice_mask));

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[PATCH 1/2] drm/i915/cnl: Add support slice/subslice/eu configs

[Rodrigo Vivi]

From: Ben Widawsky <ben@bwidawsk.net>

Cannonlake Slice and Subslice information has changed.

This patch initially provided by Ben adds the proper sseu
initialization.

v2: This v2 done by Rodrigo includes:
    - Fix on Total slices count by avoiding [1][2] and [2][2].
    - Inclusion of EU Per Subslice.
    - Commit message.
v3: This v3 done by Rodrigo includes:
    - Handle all possible bits and extra fuse register.
    - Use INTEL_GEN macro.
    - Fully assume uniform distribution so remove union
      with eu_per_subslice and add proper the comment.
v4: This v4 done by Rodrigo includes:
    - Consider all bits available: 6 bits for slices [27:22]
      and 4 for subslices [21:18].

Cc: Oscar Mateo <oscar.mateo@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h          |  8 +++++++
 drivers/gpu/drm/i915/intel_device_info.c | 37 +++++++++++++++++++++++++++++++-
 2 files changed, 44 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 94b40a469afd..9f4b8faf2982 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2730,6 +2730,11 @@ enum i915_power_well_id {
 #define   GEN9_F2_SS_DIS_SHIFT		20
 #define   GEN9_F2_SS_DIS_MASK		(0xf << GEN9_F2_SS_DIS_SHIFT)
 
+#define   GEN10_F2_S_ENA_SHIFT		22
+#define   GEN10_F2_S_ENA_MASK		(0x3f << GEN10_F2_S_ENA_SHIFT)
+#define   GEN10_F2_SS_DIS_SHIFT		18
+#define   GEN10_F2_SS_DIS_MASK		(0xf << GEN10_F2_SS_DIS_SHIFT)
+
 #define GEN8_EU_DISABLE0		_MMIO(0x9134)
 #define   GEN8_EU_DIS0_S0_MASK		0xffffff
 #define   GEN8_EU_DIS0_S1_SHIFT		24
@@ -2745,6 +2750,9 @@ enum i915_power_well_id {
 
 #define GEN9_EU_DISABLE(slice)		_MMIO(0x9134 + (slice)*0x4)
 
+#define GEN10_EU_DISABLE3		_MMIO(0x9140)
+#define   GEN10_EU_DIS_SS_MASK		0xff
+
 #define GEN6_BSD_SLEEP_PSMI_CONTROL	_MMIO(0x12050)
 #define   GEN6_BSD_SLEEP_MSG_DISABLE	(1 << 0)
 #define   GEN6_BSD_SLEEP_FLUSH_DISABLE	(1 << 2)
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 43831b09b47a..85693811c1b0 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -82,6 +82,39 @@ void intel_device_info_dump(struct drm_i915_private *dev_priv)
 #undef PRINT_FLAG
 }
 
+static void gen10_sseu_info_init(struct drm_i915_private *dev_priv)
+{
+	struct sseu_dev_info *sseu = &mkwrite_device_info(dev_priv)->sseu;
+	const u32 fuse2 = I915_READ(GEN8_FUSE2);
+
+	sseu->slice_mask = (fuse2 & GEN10_F2_S_ENA_MASK) >>
+			    GEN10_F2_S_ENA_SHIFT;
+	sseu->subslice_mask = (1 << 3) - 1;
+	sseu->subslice_mask &= ~((fuse2 & GEN10_F2_SS_DIS_MASK) >>
+				 GEN10_F2_SS_DIS_SHIFT);
+
+	sseu->eu_total = hweight32(~I915_READ(GEN8_EU_DISABLE0));
+	sseu->eu_total += hweight32(~I915_READ(GEN8_EU_DISABLE1));
+	sseu->eu_total += hweight32(~I915_READ(GEN8_EU_DISABLE2));
+	sseu->eu_total += hweight8(~(I915_READ(GEN10_EU_DISABLE3) &
+				     GEN10_EU_DIS_SS_MASK));
+
+	/*
+	 * CNL is expected to always have a uniform distribution
+	 * of EU across subslices with the exception that any one
+	 * EU in any one subslice may be fused off for die
+	 * recovery.
+	 */
+	sseu->eu_per_subslice = sseu_subslice_total(sseu) ?
+				DIV_ROUND_UP(sseu->eu_total,
+					     sseu_subslice_total(sseu)) : 0;
+
+	/* No restrictions on Power Gating */
+	sseu->has_slice_pg = 1;
+	sseu->has_subslice_pg = 1;
+	sseu->has_eu_pg = 1;
+}
+
 static void cherryview_sseu_info_init(struct drm_i915_private *dev_priv)
 {
 	struct sseu_dev_info *sseu = &mkwrite_device_info(dev_priv)->sseu;
@@ -409,8 +442,10 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
 		cherryview_sseu_info_init(dev_priv);
 	else if (IS_BROADWELL(dev_priv))
 		broadwell_sseu_info_init(dev_priv);
-	else if (INTEL_INFO(dev_priv)->gen >= 9)
+	else if (INTEL_GEN(dev_priv) == 9)
 		gen9_sseu_info_init(dev_priv);
+	else if (INTEL_GEN(dev_priv) >= 10)
+		gen10_sseu_info_init(dev_priv);
 
 	DRM_DEBUG_DRIVER("slice mask: %04x\n", info->sseu.slice_mask);
 	DRM_DEBUG_DRIVER("slice total: %u\n", hweight8(info->sseu.slice_mask));
-- 
2.13.5

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Re: [PATCH 1/2] drm/i915/cnl: Add support slice/subslice/eu configs

[Oscar Mateo]

On 09/19/2017 02:02 PM, Rodrigo Vivi wrote:
> From: Ben Widawsky <ben@bwidawsk.net>
>
> Cannonlake Slice and Subslice information has changed.
>
> This patch initially provided by Ben adds the proper sseu
> initialization.
>
> v2: This v2 done by Rodrigo includes:
>      - Fix on Total slices count by avoiding [1][2] and [2][2].
>      - Inclusion of EU Per Subslice.
>      - Commit message.
> v3: This v3 done by Rodrigo includes:
>      - Handle all possible bits and extra fuse register.
>      - Use INTEL_GEN macro.
>      - Fully assume uniform distribution so remove union
>        with eu_per_subslice and add proper the comment.
> v4: This v4 done by Rodrigo includes:
>      - Consider all bits available: 6 bits for slices [27:22]
>        and 4 for subslices [21:18].
>
> Cc: Oscar Mateo <oscar.mateo@intel.com>
> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
>   drivers/gpu/drm/i915/i915_reg.h          |  8 +++++++
>   drivers/gpu/drm/i915/intel_device_info.c | 37 +++++++++++++++++++++++++++++++-
>   2 files changed, 44 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 94b40a469afd..9f4b8faf2982 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2730,6 +2730,11 @@ enum i915_power_well_id {
>   #define   GEN9_F2_SS_DIS_SHIFT		20
>   #define   GEN9_F2_SS_DIS_MASK		(0xf << GEN9_F2_SS_DIS_SHIFT)
>   
> +#define   GEN10_F2_S_ENA_SHIFT		22
> +#define   GEN10_F2_S_ENA_MASK		(0x3f << GEN10_F2_S_ENA_SHIFT)
> +#define   GEN10_F2_SS_DIS_SHIFT		18
> +#define   GEN10_F2_SS_DIS_MASK		(0xf << GEN10_F2_SS_DIS_SHIFT)

Hmmmm... I thought you were going to read less registers for the EU 
count, but yes, this also works :)

> +
>   #define GEN8_EU_DISABLE0		_MMIO(0x9134)
>   #define   GEN8_EU_DIS0_S0_MASK		0xffffff
>   #define   GEN8_EU_DIS0_S1_SHIFT		24
> @@ -2745,6 +2750,9 @@ enum i915_power_well_id {
>   
>   #define GEN9_EU_DISABLE(slice)		_MMIO(0x9134 + (slice)*0x4)
>   
> +#define GEN10_EU_DISABLE3		_MMIO(0x9140)
> +#define   GEN10_EU_DIS_SS_MASK		0xff
> +
>   #define GEN6_BSD_SLEEP_PSMI_CONTROL	_MMIO(0x12050)
>   #define   GEN6_BSD_SLEEP_MSG_DISABLE	(1 << 0)
>   #define   GEN6_BSD_SLEEP_FLUSH_DISABLE	(1 << 2)
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index 43831b09b47a..85693811c1b0 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -82,6 +82,39 @@ void intel_device_info_dump(struct drm_i915_private *dev_priv)
>   #undef PRINT_FLAG
>   }
>   
> +static void gen10_sseu_info_init(struct drm_i915_private *dev_priv)
> +{
> +	struct sseu_dev_info *sseu = &mkwrite_device_info(dev_priv)->sseu;
> +	const u32 fuse2 = I915_READ(GEN8_FUSE2);
> +
> +	sseu->slice_mask = (fuse2 & GEN10_F2_S_ENA_MASK) >>
> +			    GEN10_F2_S_ENA_SHIFT;
> +	sseu->subslice_mask = (1 << 3) - 1;

But this should be now: (1 << 4) - 1 (or maybe use a local ss_max for 
clarity, like in the other patch)

> +	sseu->subslice_mask &= ~((fuse2 & GEN10_F2_SS_DIS_MASK) >>
> +				 GEN10_F2_SS_DIS_SHIFT);
> +
> +	sseu->eu_total = hweight32(~I915_READ(GEN8_EU_DISABLE0));
> +	sseu->eu_total += hweight32(~I915_READ(GEN8_EU_DISABLE1));
> +	sseu->eu_total += hweight32(~I915_READ(GEN8_EU_DISABLE2));
> +	sseu->eu_total += hweight8(~(I915_READ(GEN10_EU_DISABLE3) &
> +				     GEN10_EU_DIS_SS_MASK));
> +
> +	/*
> +	 * CNL is expected to always have a uniform distribution
> +	 * of EU across subslices with the exception that any one
> +	 * EU in any one subslice may be fused off for die
> +	 * recovery.
> +	 */
> +	sseu->eu_per_subslice = sseu_subslice_total(sseu) ?
> +				DIV_ROUND_UP(sseu->eu_total,
> +					     sseu_subslice_total(sseu)) : 0;
> +
> +	/* No restrictions on Power Gating */
> +	sseu->has_slice_pg = 1;
> +	sseu->has_subslice_pg = 1;
> +	sseu->has_eu_pg = 1;
> +}
> +
>   static void cherryview_sseu_info_init(struct drm_i915_private *dev_priv)
>   {
>   	struct sseu_dev_info *sseu = &mkwrite_device_info(dev_priv)->sseu;
> @@ -409,8 +442,10 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
>   		cherryview_sseu_info_init(dev_priv);
>   	else if (IS_BROADWELL(dev_priv))
>   		broadwell_sseu_info_init(dev_priv);
> -	else if (INTEL_INFO(dev_priv)->gen >= 9)
> +	else if (INTEL_GEN(dev_priv) == 9)
>   		gen9_sseu_info_init(dev_priv);
> +	else if (INTEL_GEN(dev_priv) >= 10)
> +		gen10_sseu_info_init(dev_priv);
>   
>   	DRM_DEBUG_DRIVER("slice mask: %04x\n", info->sseu.slice_mask);
>   	DRM_DEBUG_DRIVER("slice total: %u\n", hweight8(info->sseu.slice_mask));

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