From: Oscar Mateo <oscar.mateo@intel.com>
To: Rodrigo Vivi <rodrigo.vivi@intel.com>, intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/i915/cnl: WaForceContextSaveRestoreNonCoherent
Date: Wed, 23 Aug 2017 13:00:19 -0700 [thread overview]
Message-ID: <cf9cb1aa-c7e3-4ab8-6419-03f0b4e4eb48@intel.com> (raw)
In-Reply-To: <20170822232715.3220-1-rodrigo.vivi@intel.com>
On 08/22/2017 04:27 PM, Rodrigo Vivi wrote:
> To avoid a potential hang condition with TLB invalidation
> we need to enable masked bit 5 of MMIO 0xE5F0 at boot.
>
> Same workaround was in place for previous platforms,
> but the change for CNL is more on the register offset.
"but the register offset has changed for CNL"?
> But also BSpec doesn't mention the bit 15 as set on gen9
> platforms and mark bit as reserved on CNL.
>
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Cc: Oscar Mateo <oscar.mateo@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/intel_engine_cs.c | 4 ++++
> 2 files changed, 5 insertions(+)
Reviewed-by: Oscar Mateo <oscar.mateo@intel.com>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index d4ecb1905ad8..f31fab2651fb 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7024,6 +7024,7 @@ enum {
>
> /* GEN8 chicken */
> #define HDC_CHICKEN0 _MMIO(0x7300)
> +#define CNL_HDC_CHICKEN0 _MMIO(0xE5F0)
> #define HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE (1<<15)
> #define HDC_FENCE_DEST_SLM_DISABLE (1<<14)
> #define HDC_DONOT_FETCH_MEM_WHEN_MASKED (1<<11)
> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
> index d23f18874309..26c35ce5f240 100644
> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> @@ -1070,6 +1070,10 @@ static int cnl_init_workarounds(struct intel_engine_cs *engine)
> struct drm_i915_private *dev_priv = engine->i915;
> int ret;
>
> + /* WaForceContextSaveRestoreNonCoherent:cnl */
> + WA_SET_BIT_MASKED(CNL_HDC_CHICKEN0,
> + HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT);
> +
> /* WaDisableReplayBufferBankArbitrationOptimization:cnl */
> WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
> GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
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next prev parent reply other threads:[~2017-08-23 20:00 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-08-22 23:27 [PATCH] drm/i915/cnl: WaForceContextSaveRestoreNonCoherent Rodrigo Vivi
2017-08-22 23:43 ` ✓ Fi.CI.BAT: success for " Patchwork
2017-08-23 20:00 ` Oscar Mateo [this message]
2017-08-23 20:35 ` [PATCH] " Rodrigo Vivi
2017-08-23 21:48 ` Rodrigo Vivi
2017-08-23 21:30 ` ✓ Fi.CI.BAT: success for drm/i915/cnl: WaForceContextSaveRestoreNonCoherent (rev2) Patchwork
2017-09-27 9:19 ` [PATCH] drm/i915/cnl: WaForceContextSaveRestoreNonCoherent Chris Wilson
2017-09-27 10:37 ` Mika Kuoppala
2017-09-27 17:37 ` Oscar Mateo
2017-09-27 17:42 ` Chris Wilson
2017-09-28 9:46 ` Chris Wilson
2017-09-28 20:56 ` Oscar Mateo
2017-09-28 21:38 ` Oscar Mateo
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