* [PATCH 00/18] drm/i915: hdmi/dp audio rework
@ 2014-10-03 12:43 Jani Nikula
2014-10-03 12:43 ` [PATCH 01/18] drm/i915: add new intel audio file to group DP/HDMI audio Jani Nikula
` (17 more replies)
0 siblings, 18 replies; 20+ messages in thread
From: Jani Nikula @ 2014-10-03 12:43 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, shuang.he
So I set out to split out the audio stuff into its own file, doing some
cleanups and maybe fixing a bug or two along the way. Here's the first
18 patches. ;)
There's still some issues with vblank waits that need to be revisited,
but I wanted to get early feedback anyway. So disregard those bits for
now. Everything else should be close to ready.
This has only gotten light testing, in particular no testing over DP
audio yet because I don't have a sink that supports it. Also no testing
on hsw/bdw yet.
BR,
Jani.
Jani Nikula (18):
drm/i915: add new intel audio file to group DP/HDMI audio
drm/i915/audio: constify hdmi audio clock struct
drm/i915/audio: beat some sense into the variable types and names
drm/i915: pass intel_encoder to intel_write_eld
drm/i915/audio: pass intel_encoder on to platform specific ELD
functions
drm/i915/audio: set ELD Conn_Type at one place
drm/i915/ddi: write ELD where it's supposed to be done
drm/i915: introduce intel_audio_codec_{enable,disable}
drm/i915/audio: remove misleading checks for !eld[0]
drm/i915: clean up and clarify audio related register defines
drm/i915: rewrite hsw/bdw audio codec enable/disable sequences
drm/i915/audio: rewrite vlv/chv and gen 5-7 audio codec enable
sequence
drm/i915/audio: add vlv/chv/gen5-7 audio codec disable sequence
drm/i915: enable audio codec after port
drm/i915/audio: add audio codec disable on g4x
drm/i915/audio: add audio codec enable debug log for g4x
drm/i915: make pipe/port based audio valid accessors easier to use
drm/i915/audio: add DOC comment describing HDA over HDMI/DP
drivers/gpu/drm/i915/Makefile | 3 +-
drivers/gpu/drm/i915/i915_drv.h | 9 +-
drivers/gpu/drm/i915/i915_reg.h | 181 +++++++--------
drivers/gpu/drm/i915/intel_audio.c | 435 +++++++++++++++++++++++++++++++++++
drivers/gpu/drm/i915/intel_ddi.c | 26 +--
drivers/gpu/drm/i915/intel_display.c | 321 +-------------------------
drivers/gpu/drm/i915/intel_dp.c | 17 +-
drivers/gpu/drm/i915/intel_drv.h | 8 +-
drivers/gpu/drm/i915/intel_hdmi.c | 19 +-
9 files changed, 564 insertions(+), 455 deletions(-)
create mode 100644 drivers/gpu/drm/i915/intel_audio.c
--
1.9.1
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH 01/18] drm/i915: add new intel audio file to group DP/HDMI audio
2014-10-03 12:43 [PATCH 00/18] drm/i915: hdmi/dp audio rework Jani Nikula
@ 2014-10-03 12:43 ` Jani Nikula
2014-10-03 12:43 ` [PATCH 02/18] drm/i915/audio: constify hdmi audio clock struct Jani Nikula
` (16 subsequent siblings)
17 siblings, 0 replies; 20+ messages in thread
From: Jani Nikula @ 2014-10-03 12:43 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, shuang.he
In preparation for some additional cleanup. No functional changes.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/Makefile | 3 +-
drivers/gpu/drm/i915/intel_audio.c | 352 +++++++++++++++++++++++++++++++++++
drivers/gpu/drm/i915/intel_display.c | 321 +-------------------------------
drivers/gpu/drm/i915/intel_drv.h | 8 +-
4 files changed, 363 insertions(+), 321 deletions(-)
create mode 100644 drivers/gpu/drm/i915/intel_audio.c
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 3a6bce047f6f..3be472d9da1c 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -43,7 +43,8 @@ i915-y += intel_renderstate_gen6.o \
intel_renderstate_gen8.o
# modesetting core code
-i915-y += intel_bios.o \
+i915-y += intel_audio.o \
+ intel_bios.o \
intel_display.o \
intel_frontbuffer.o \
intel_modes.o \
diff --git a/drivers/gpu/drm/i915/intel_audio.c b/drivers/gpu/drm/i915/intel_audio.c
new file mode 100644
index 000000000000..461363e881b3
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_audio.c
@@ -0,0 +1,352 @@
+/*
+ * Copyright © 2014 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <linux/kernel.h>
+
+#include <drm/drmP.h>
+#include <drm/drm_edid.h>
+#include "intel_drv.h"
+#include "i915_drv.h"
+
+static struct {
+ int clock;
+ u32 config;
+} hdmi_audio_clock[] = {
+ { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
+ { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
+ { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
+ { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
+ { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
+ { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
+ { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
+ { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
+ { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
+ { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
+};
+
+/* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
+static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
+ if (mode->clock == hdmi_audio_clock[i].clock)
+ break;
+ }
+
+ if (i == ARRAY_SIZE(hdmi_audio_clock)) {
+ DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock);
+ i = 1;
+ }
+
+ DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
+ hdmi_audio_clock[i].clock,
+ hdmi_audio_clock[i].config);
+
+ return hdmi_audio_clock[i].config;
+}
+
+static bool intel_eld_uptodate(struct drm_connector *connector,
+ int reg_eldv, uint32_t bits_eldv,
+ int reg_elda, uint32_t bits_elda,
+ int reg_edid)
+{
+ struct drm_i915_private *dev_priv = connector->dev->dev_private;
+ uint8_t *eld = connector->eld;
+ uint32_t i;
+
+ i = I915_READ(reg_eldv);
+ i &= bits_eldv;
+
+ if (!eld[0])
+ return !i;
+
+ if (!i)
+ return false;
+
+ i = I915_READ(reg_elda);
+ i &= ~bits_elda;
+ I915_WRITE(reg_elda, i);
+
+ for (i = 0; i < eld[2]; i++)
+ if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
+ return false;
+
+ return true;
+}
+
+static void g4x_write_eld(struct drm_connector *connector,
+ struct drm_crtc *crtc,
+ struct drm_display_mode *mode)
+{
+ struct drm_i915_private *dev_priv = connector->dev->dev_private;
+ uint8_t *eld = connector->eld;
+ uint32_t eldv;
+ uint32_t len;
+ uint32_t i;
+
+ i = I915_READ(G4X_AUD_VID_DID);
+
+ if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
+ eldv = G4X_ELDV_DEVCL_DEVBLC;
+ else
+ eldv = G4X_ELDV_DEVCTG;
+
+ if (intel_eld_uptodate(connector,
+ G4X_AUD_CNTL_ST, eldv,
+ G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
+ G4X_HDMIW_HDMIEDID))
+ return;
+
+ i = I915_READ(G4X_AUD_CNTL_ST);
+ i &= ~(eldv | G4X_ELD_ADDR);
+ len = (i >> 9) & 0x1f; /* ELD buffer size */
+ I915_WRITE(G4X_AUD_CNTL_ST, i);
+
+ if (!eld[0])
+ return;
+
+ len = min_t(uint8_t, eld[2], len);
+ DRM_DEBUG_DRIVER("ELD size %d\n", len);
+ for (i = 0; i < len; i++)
+ I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
+
+ i = I915_READ(G4X_AUD_CNTL_ST);
+ i |= eldv;
+ I915_WRITE(G4X_AUD_CNTL_ST, i);
+}
+
+static void haswell_write_eld(struct drm_connector *connector,
+ struct drm_crtc *crtc,
+ struct drm_display_mode *mode)
+{
+ struct drm_i915_private *dev_priv = connector->dev->dev_private;
+ uint8_t *eld = connector->eld;
+ uint32_t eldv;
+ uint32_t i;
+ int len;
+ int pipe = to_intel_crtc(crtc)->pipe;
+ int tmp;
+
+ int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
+ int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
+ int aud_config = HSW_AUD_CFG(pipe);
+ int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
+
+ /* Audio output enable */
+ DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
+ tmp = I915_READ(aud_cntrl_st2);
+ tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
+ I915_WRITE(aud_cntrl_st2, tmp);
+ POSTING_READ(aud_cntrl_st2);
+
+ assert_pipe_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
+
+ /* Set ELD valid state */
+ tmp = I915_READ(aud_cntrl_st2);
+ DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
+ tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
+ I915_WRITE(aud_cntrl_st2, tmp);
+ tmp = I915_READ(aud_cntrl_st2);
+ DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
+
+ /* Enable HDMI mode */
+ tmp = I915_READ(aud_config);
+ DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
+ /* clear N_programing_enable and N_value_index */
+ tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
+ I915_WRITE(aud_config, tmp);
+
+ DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
+
+ eldv = AUDIO_ELD_VALID_A << (pipe * 4);
+
+ if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
+ DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
+ eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
+ I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
+ } else {
+ I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
+ }
+
+ if (intel_eld_uptodate(connector,
+ aud_cntrl_st2, eldv,
+ aud_cntl_st, IBX_ELD_ADDRESS,
+ hdmiw_hdmiedid))
+ return;
+
+ i = I915_READ(aud_cntrl_st2);
+ i &= ~eldv;
+ I915_WRITE(aud_cntrl_st2, i);
+
+ if (!eld[0])
+ return;
+
+ i = I915_READ(aud_cntl_st);
+ i &= ~IBX_ELD_ADDRESS;
+ I915_WRITE(aud_cntl_st, i);
+ i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
+ DRM_DEBUG_DRIVER("port num:%d\n", i);
+
+ len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
+ DRM_DEBUG_DRIVER("ELD size %d\n", len);
+ for (i = 0; i < len; i++)
+ I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
+
+ i = I915_READ(aud_cntrl_st2);
+ i |= eldv;
+ I915_WRITE(aud_cntrl_st2, i);
+
+}
+
+static void ironlake_write_eld(struct drm_connector *connector,
+ struct drm_crtc *crtc,
+ struct drm_display_mode *mode)
+{
+ struct drm_i915_private *dev_priv = connector->dev->dev_private;
+ uint8_t *eld = connector->eld;
+ uint32_t eldv;
+ uint32_t i;
+ int len;
+ int hdmiw_hdmiedid;
+ int aud_config;
+ int aud_cntl_st;
+ int aud_cntrl_st2;
+ int pipe = to_intel_crtc(crtc)->pipe;
+
+ if (HAS_PCH_IBX(connector->dev)) {
+ hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
+ aud_config = IBX_AUD_CFG(pipe);
+ aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
+ aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
+ } else if (IS_VALLEYVIEW(connector->dev)) {
+ hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
+ aud_config = VLV_AUD_CFG(pipe);
+ aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
+ aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
+ } else {
+ hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
+ aud_config = CPT_AUD_CFG(pipe);
+ aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
+ aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
+ }
+
+ DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
+
+ if (IS_VALLEYVIEW(connector->dev)) {
+ struct intel_encoder *intel_encoder;
+ struct intel_digital_port *intel_dig_port;
+
+ intel_encoder = intel_attached_encoder(connector);
+ intel_dig_port = enc_to_dig_port(&intel_encoder->base);
+ i = intel_dig_port->port;
+ } else {
+ i = I915_READ(aud_cntl_st);
+ i = (i >> 29) & DIP_PORT_SEL_MASK;
+ /* DIP_Port_Select, 0x1 = PortB */
+ }
+
+ if (!i) {
+ DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
+ /* operate blindly on all ports */
+ eldv = IBX_ELD_VALIDB;
+ eldv |= IBX_ELD_VALIDB << 4;
+ eldv |= IBX_ELD_VALIDB << 8;
+ } else {
+ DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
+ eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
+ }
+
+ if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
+ DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
+ eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
+ I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
+ } else {
+ I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
+ }
+
+ if (intel_eld_uptodate(connector,
+ aud_cntrl_st2, eldv,
+ aud_cntl_st, IBX_ELD_ADDRESS,
+ hdmiw_hdmiedid))
+ return;
+
+ i = I915_READ(aud_cntrl_st2);
+ i &= ~eldv;
+ I915_WRITE(aud_cntrl_st2, i);
+
+ if (!eld[0])
+ return;
+
+ i = I915_READ(aud_cntl_st);
+ i &= ~IBX_ELD_ADDRESS;
+ I915_WRITE(aud_cntl_st, i);
+
+ len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
+ DRM_DEBUG_DRIVER("ELD size %d\n", len);
+ for (i = 0; i < len; i++)
+ I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
+
+ i = I915_READ(aud_cntrl_st2);
+ i |= eldv;
+ I915_WRITE(aud_cntrl_st2, i);
+}
+
+void intel_write_eld(struct drm_encoder *encoder,
+ struct drm_display_mode *mode)
+{
+ struct drm_crtc *crtc = encoder->crtc;
+ struct drm_connector *connector;
+ struct drm_device *dev = encoder->dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+
+ connector = drm_select_eld(encoder, mode);
+ if (!connector)
+ return;
+
+ DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
+ connector->base.id,
+ connector->name,
+ connector->encoder->base.id,
+ connector->encoder->name);
+
+ connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
+
+ if (dev_priv->display.write_eld)
+ dev_priv->display.write_eld(connector, crtc, mode);
+}
+
+/* Set up chip specific audio functions */
+void intel_init_audio(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+
+ if (IS_G4X(dev))
+ dev_priv->display.write_eld = g4x_write_eld;
+ else if (IS_VALLEYVIEW(dev))
+ dev_priv->display.write_eld = ironlake_write_eld;
+ else if (IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8)
+ dev_priv->display.write_eld = haswell_write_eld;
+ else if (HAS_PCH_SPLIT(dev))
+ dev_priv->display.write_eld = ironlake_write_eld;
+}
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 1936648d8aba..00d06a04ebe1 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -409,7 +409,7 @@ static void vlv_clock(int refclk, intel_clock_t *clock)
/**
* Returns whether any output on the specified pipe is of the specified type
*/
-static bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
+bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
{
struct drm_device *dev = crtc->dev;
struct intel_encoder *encoder;
@@ -7952,314 +7952,6 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
return true;
}
-static struct {
- int clock;
- u32 config;
-} hdmi_audio_clock[] = {
- { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
- { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
- { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
- { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
- { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
- { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
- { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
- { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
- { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
- { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
-};
-
-/* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
-static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode)
-{
- int i;
-
- for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
- if (mode->clock == hdmi_audio_clock[i].clock)
- break;
- }
-
- if (i == ARRAY_SIZE(hdmi_audio_clock)) {
- DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock);
- i = 1;
- }
-
- DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
- hdmi_audio_clock[i].clock,
- hdmi_audio_clock[i].config);
-
- return hdmi_audio_clock[i].config;
-}
-
-static bool intel_eld_uptodate(struct drm_connector *connector,
- int reg_eldv, uint32_t bits_eldv,
- int reg_elda, uint32_t bits_elda,
- int reg_edid)
-{
- struct drm_i915_private *dev_priv = connector->dev->dev_private;
- uint8_t *eld = connector->eld;
- uint32_t i;
-
- i = I915_READ(reg_eldv);
- i &= bits_eldv;
-
- if (!eld[0])
- return !i;
-
- if (!i)
- return false;
-
- i = I915_READ(reg_elda);
- i &= ~bits_elda;
- I915_WRITE(reg_elda, i);
-
- for (i = 0; i < eld[2]; i++)
- if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
- return false;
-
- return true;
-}
-
-static void g4x_write_eld(struct drm_connector *connector,
- struct drm_crtc *crtc,
- struct drm_display_mode *mode)
-{
- struct drm_i915_private *dev_priv = connector->dev->dev_private;
- uint8_t *eld = connector->eld;
- uint32_t eldv;
- uint32_t len;
- uint32_t i;
-
- i = I915_READ(G4X_AUD_VID_DID);
-
- if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
- eldv = G4X_ELDV_DEVCL_DEVBLC;
- else
- eldv = G4X_ELDV_DEVCTG;
-
- if (intel_eld_uptodate(connector,
- G4X_AUD_CNTL_ST, eldv,
- G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
- G4X_HDMIW_HDMIEDID))
- return;
-
- i = I915_READ(G4X_AUD_CNTL_ST);
- i &= ~(eldv | G4X_ELD_ADDR);
- len = (i >> 9) & 0x1f; /* ELD buffer size */
- I915_WRITE(G4X_AUD_CNTL_ST, i);
-
- if (!eld[0])
- return;
-
- len = min_t(uint8_t, eld[2], len);
- DRM_DEBUG_DRIVER("ELD size %d\n", len);
- for (i = 0; i < len; i++)
- I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
-
- i = I915_READ(G4X_AUD_CNTL_ST);
- i |= eldv;
- I915_WRITE(G4X_AUD_CNTL_ST, i);
-}
-
-static void haswell_write_eld(struct drm_connector *connector,
- struct drm_crtc *crtc,
- struct drm_display_mode *mode)
-{
- struct drm_i915_private *dev_priv = connector->dev->dev_private;
- uint8_t *eld = connector->eld;
- uint32_t eldv;
- uint32_t i;
- int len;
- int pipe = to_intel_crtc(crtc)->pipe;
- int tmp;
-
- int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
- int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
- int aud_config = HSW_AUD_CFG(pipe);
- int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
-
- /* Audio output enable */
- DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
- tmp = I915_READ(aud_cntrl_st2);
- tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
- I915_WRITE(aud_cntrl_st2, tmp);
- POSTING_READ(aud_cntrl_st2);
-
- assert_pipe_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
-
- /* Set ELD valid state */
- tmp = I915_READ(aud_cntrl_st2);
- DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
- tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
- I915_WRITE(aud_cntrl_st2, tmp);
- tmp = I915_READ(aud_cntrl_st2);
- DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
-
- /* Enable HDMI mode */
- tmp = I915_READ(aud_config);
- DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
- /* clear N_programing_enable and N_value_index */
- tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
- I915_WRITE(aud_config, tmp);
-
- DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
-
- eldv = AUDIO_ELD_VALID_A << (pipe * 4);
-
- if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
- DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
- eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
- I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
- } else {
- I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
- }
-
- if (intel_eld_uptodate(connector,
- aud_cntrl_st2, eldv,
- aud_cntl_st, IBX_ELD_ADDRESS,
- hdmiw_hdmiedid))
- return;
-
- i = I915_READ(aud_cntrl_st2);
- i &= ~eldv;
- I915_WRITE(aud_cntrl_st2, i);
-
- if (!eld[0])
- return;
-
- i = I915_READ(aud_cntl_st);
- i &= ~IBX_ELD_ADDRESS;
- I915_WRITE(aud_cntl_st, i);
- i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
- DRM_DEBUG_DRIVER("port num:%d\n", i);
-
- len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
- DRM_DEBUG_DRIVER("ELD size %d\n", len);
- for (i = 0; i < len; i++)
- I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
-
- i = I915_READ(aud_cntrl_st2);
- i |= eldv;
- I915_WRITE(aud_cntrl_st2, i);
-
-}
-
-static void ironlake_write_eld(struct drm_connector *connector,
- struct drm_crtc *crtc,
- struct drm_display_mode *mode)
-{
- struct drm_i915_private *dev_priv = connector->dev->dev_private;
- uint8_t *eld = connector->eld;
- uint32_t eldv;
- uint32_t i;
- int len;
- int hdmiw_hdmiedid;
- int aud_config;
- int aud_cntl_st;
- int aud_cntrl_st2;
- int pipe = to_intel_crtc(crtc)->pipe;
-
- if (HAS_PCH_IBX(connector->dev)) {
- hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
- aud_config = IBX_AUD_CFG(pipe);
- aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
- aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
- } else if (IS_VALLEYVIEW(connector->dev)) {
- hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
- aud_config = VLV_AUD_CFG(pipe);
- aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
- aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
- } else {
- hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
- aud_config = CPT_AUD_CFG(pipe);
- aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
- aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
- }
-
- DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
-
- if (IS_VALLEYVIEW(connector->dev)) {
- struct intel_encoder *intel_encoder;
- struct intel_digital_port *intel_dig_port;
-
- intel_encoder = intel_attached_encoder(connector);
- intel_dig_port = enc_to_dig_port(&intel_encoder->base);
- i = intel_dig_port->port;
- } else {
- i = I915_READ(aud_cntl_st);
- i = (i >> 29) & DIP_PORT_SEL_MASK;
- /* DIP_Port_Select, 0x1 = PortB */
- }
-
- if (!i) {
- DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
- /* operate blindly on all ports */
- eldv = IBX_ELD_VALIDB;
- eldv |= IBX_ELD_VALIDB << 4;
- eldv |= IBX_ELD_VALIDB << 8;
- } else {
- DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
- eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
- }
-
- if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
- DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
- eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
- I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
- } else {
- I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
- }
-
- if (intel_eld_uptodate(connector,
- aud_cntrl_st2, eldv,
- aud_cntl_st, IBX_ELD_ADDRESS,
- hdmiw_hdmiedid))
- return;
-
- i = I915_READ(aud_cntrl_st2);
- i &= ~eldv;
- I915_WRITE(aud_cntrl_st2, i);
-
- if (!eld[0])
- return;
-
- i = I915_READ(aud_cntl_st);
- i &= ~IBX_ELD_ADDRESS;
- I915_WRITE(aud_cntl_st, i);
-
- len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
- DRM_DEBUG_DRIVER("ELD size %d\n", len);
- for (i = 0; i < len; i++)
- I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
-
- i = I915_READ(aud_cntrl_st2);
- i |= eldv;
- I915_WRITE(aud_cntrl_st2, i);
-}
-
-void intel_write_eld(struct drm_encoder *encoder,
- struct drm_display_mode *mode)
-{
- struct drm_crtc *crtc = encoder->crtc;
- struct drm_connector *connector;
- struct drm_device *dev = encoder->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
-
- connector = drm_select_eld(encoder, mode);
- if (!connector)
- return;
-
- DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
- connector->base.id,
- connector->name,
- connector->encoder->base.id,
- connector->encoder->name);
-
- connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
-
- if (dev_priv->display.write_eld)
- dev_priv->display.write_eld(connector, crtc, mode);
-}
-
static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
{
struct drm_device *dev = crtc->dev;
@@ -12567,33 +12259,25 @@ static void intel_init_display(struct drm_device *dev)
dev_priv->display.get_display_clock_speed =
i830_get_display_clock_speed;
- if (IS_G4X(dev)) {
- dev_priv->display.write_eld = g4x_write_eld;
- } else if (IS_GEN5(dev)) {
+ if (IS_GEN5(dev)) {
dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
- dev_priv->display.write_eld = ironlake_write_eld;
} else if (IS_GEN6(dev)) {
dev_priv->display.fdi_link_train = gen6_fdi_link_train;
- dev_priv->display.write_eld = ironlake_write_eld;
dev_priv->display.modeset_global_resources =
snb_modeset_global_resources;
} else if (IS_IVYBRIDGE(dev)) {
/* FIXME: detect B0+ stepping and use auto training */
dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
- dev_priv->display.write_eld = ironlake_write_eld;
dev_priv->display.modeset_global_resources =
ivb_modeset_global_resources;
} else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
dev_priv->display.fdi_link_train = hsw_fdi_link_train;
- dev_priv->display.write_eld = haswell_write_eld;
dev_priv->display.modeset_global_resources =
haswell_modeset_global_resources;
} else if (IS_VALLEYVIEW(dev)) {
dev_priv->display.modeset_global_resources =
valleyview_modeset_global_resources;
- dev_priv->display.write_eld = ironlake_write_eld;
} else if (INTEL_INFO(dev)->gen >= 9) {
- dev_priv->display.write_eld = haswell_write_eld;
dev_priv->display.modeset_global_resources =
haswell_modeset_global_resources;
}
@@ -12848,6 +12532,7 @@ void intel_modeset_init(struct drm_device *dev)
return;
intel_init_display(dev);
+ intel_init_audio(dev);
if (IS_GEN2(dev)) {
dev->mode_config.max_width = 2048;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index ffbf38d9b536..e14c88f9f4d2 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -839,6 +839,11 @@ void intel_frontbuffer_flip(struct drm_device *dev,
void intel_fb_obj_flush(struct drm_i915_gem_object *obj, bool retire);
+/* intel_audio.c */
+void intel_init_audio(struct drm_device *dev);
+void intel_write_eld(struct drm_encoder *encoder,
+ struct drm_display_mode *mode);
+
/* intel_display.c */
const char *intel_output_name(int output);
bool intel_has_pending_fb_unpin(struct drm_device *dev);
@@ -864,6 +869,7 @@ int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
struct drm_file *file_priv);
enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
enum pipe pipe);
+bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
static inline void
intel_wait_for_vblank(struct drm_device *dev, int pipe)
{
@@ -915,8 +921,6 @@ void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
#define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
#define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
-void intel_write_eld(struct drm_encoder *encoder,
- struct drm_display_mode *mode);
unsigned long intel_gen4_compute_page_offset(int *x, int *y,
unsigned int tiling_mode,
unsigned int bpp,
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 02/18] drm/i915/audio: constify hdmi audio clock struct
2014-10-03 12:43 [PATCH 00/18] drm/i915: hdmi/dp audio rework Jani Nikula
2014-10-03 12:43 ` [PATCH 01/18] drm/i915: add new intel audio file to group DP/HDMI audio Jani Nikula
@ 2014-10-03 12:43 ` Jani Nikula
2014-10-03 12:43 ` [PATCH 03/18] drm/i915/audio: beat some sense into the variable types and names Jani Nikula
` (15 subsequent siblings)
17 siblings, 0 replies; 20+ messages in thread
From: Jani Nikula @ 2014-10-03 12:43 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, shuang.he
Const is good.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/intel_audio.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_audio.c b/drivers/gpu/drm/i915/intel_audio.c
index 461363e881b3..2397ac3c9842 100644
--- a/drivers/gpu/drm/i915/intel_audio.c
+++ b/drivers/gpu/drm/i915/intel_audio.c
@@ -28,7 +28,7 @@
#include "intel_drv.h"
#include "i915_drv.h"
-static struct {
+static const struct {
int clock;
u32 config;
} hdmi_audio_clock[] = {
--
1.9.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 03/18] drm/i915/audio: beat some sense into the variable types and names
2014-10-03 12:43 [PATCH 00/18] drm/i915: hdmi/dp audio rework Jani Nikula
2014-10-03 12:43 ` [PATCH 01/18] drm/i915: add new intel audio file to group DP/HDMI audio Jani Nikula
2014-10-03 12:43 ` [PATCH 02/18] drm/i915/audio: constify hdmi audio clock struct Jani Nikula
@ 2014-10-03 12:43 ` Jani Nikula
2014-10-03 12:43 ` [PATCH 04/18] drm/i915: pass intel_encoder to intel_write_eld Jani Nikula
` (14 subsequent siblings)
17 siblings, 0 replies; 20+ messages in thread
From: Jani Nikula @ 2014-10-03 12:43 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, shuang.he
Most importantly, "i" need not be the universal variable used for
everything. No functional changes.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/intel_audio.c | 115 ++++++++++++++++++-------------------
1 file changed, 57 insertions(+), 58 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_audio.c b/drivers/gpu/drm/i915/intel_audio.c
index 2397ac3c9842..0690a948a6d3 100644
--- a/drivers/gpu/drm/i915/intel_audio.c
+++ b/drivers/gpu/drm/i915/intel_audio.c
@@ -73,20 +73,21 @@ static bool intel_eld_uptodate(struct drm_connector *connector,
{
struct drm_i915_private *dev_priv = connector->dev->dev_private;
uint8_t *eld = connector->eld;
- uint32_t i;
+ uint32_t tmp;
+ int i;
- i = I915_READ(reg_eldv);
- i &= bits_eldv;
+ tmp = I915_READ(reg_eldv);
+ tmp &= bits_eldv;
if (!eld[0])
- return !i;
+ return !tmp;
- if (!i)
+ if (!tmp)
return false;
- i = I915_READ(reg_elda);
- i &= ~bits_elda;
- I915_WRITE(reg_elda, i);
+ tmp = I915_READ(reg_elda);
+ tmp &= ~bits_elda;
+ I915_WRITE(reg_elda, tmp);
for (i = 0; i < eld[2]; i++)
if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
@@ -102,12 +103,11 @@ static void g4x_write_eld(struct drm_connector *connector,
struct drm_i915_private *dev_priv = connector->dev->dev_private;
uint8_t *eld = connector->eld;
uint32_t eldv;
- uint32_t len;
- uint32_t i;
-
- i = I915_READ(G4X_AUD_VID_DID);
+ uint32_t tmp;
+ int len, i;
- if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
+ tmp = I915_READ(G4X_AUD_VID_DID);
+ if (tmp == INTEL_AUDIO_DEVBLC || tmp == INTEL_AUDIO_DEVCL)
eldv = G4X_ELDV_DEVCL_DEVBLC;
else
eldv = G4X_ELDV_DEVCTG;
@@ -118,22 +118,22 @@ static void g4x_write_eld(struct drm_connector *connector,
G4X_HDMIW_HDMIEDID))
return;
- i = I915_READ(G4X_AUD_CNTL_ST);
- i &= ~(eldv | G4X_ELD_ADDR);
- len = (i >> 9) & 0x1f; /* ELD buffer size */
- I915_WRITE(G4X_AUD_CNTL_ST, i);
+ tmp = I915_READ(G4X_AUD_CNTL_ST);
+ tmp &= ~(eldv | G4X_ELD_ADDR);
+ len = (tmp >> 9) & 0x1f; /* ELD buffer size */
+ I915_WRITE(G4X_AUD_CNTL_ST, tmp);
if (!eld[0])
return;
- len = min_t(uint8_t, eld[2], len);
+ len = min_t(int, eld[2], len);
DRM_DEBUG_DRIVER("ELD size %d\n", len);
for (i = 0; i < len; i++)
I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
- i = I915_READ(G4X_AUD_CNTL_ST);
- i |= eldv;
- I915_WRITE(G4X_AUD_CNTL_ST, i);
+ tmp = I915_READ(G4X_AUD_CNTL_ST);
+ tmp |= eldv;
+ I915_WRITE(G4X_AUD_CNTL_ST, tmp);
}
static void haswell_write_eld(struct drm_connector *connector,
@@ -143,11 +143,10 @@ static void haswell_write_eld(struct drm_connector *connector,
struct drm_i915_private *dev_priv = connector->dev->dev_private;
uint8_t *eld = connector->eld;
uint32_t eldv;
- uint32_t i;
- int len;
- int pipe = to_intel_crtc(crtc)->pipe;
- int tmp;
-
+ uint32_t tmp;
+ int len, i;
+ enum pipe pipe = to_intel_crtc(crtc)->pipe;
+ enum port port;
int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
int aud_config = HSW_AUD_CFG(pipe);
@@ -195,28 +194,27 @@ static void haswell_write_eld(struct drm_connector *connector,
hdmiw_hdmiedid))
return;
- i = I915_READ(aud_cntrl_st2);
- i &= ~eldv;
- I915_WRITE(aud_cntrl_st2, i);
+ tmp = I915_READ(aud_cntrl_st2);
+ tmp &= ~eldv;
+ I915_WRITE(aud_cntrl_st2, tmp);
if (!eld[0])
return;
- i = I915_READ(aud_cntl_st);
- i &= ~IBX_ELD_ADDRESS;
- I915_WRITE(aud_cntl_st, i);
- i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
- DRM_DEBUG_DRIVER("port num:%d\n", i);
+ tmp = I915_READ(aud_cntl_st);
+ tmp &= ~IBX_ELD_ADDRESS;
+ I915_WRITE(aud_cntl_st, tmp);
+ port = (tmp >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
+ DRM_DEBUG_DRIVER("port num:%d\n", port);
- len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
+ len = min_t(int, eld[2], 21); /* 84 bytes of hw ELD buffer */
DRM_DEBUG_DRIVER("ELD size %d\n", len);
for (i = 0; i < len; i++)
I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
- i = I915_READ(aud_cntrl_st2);
- i |= eldv;
- I915_WRITE(aud_cntrl_st2, i);
-
+ tmp = I915_READ(aud_cntrl_st2);
+ tmp |= eldv;
+ I915_WRITE(aud_cntrl_st2, tmp);
}
static void ironlake_write_eld(struct drm_connector *connector,
@@ -226,13 +224,14 @@ static void ironlake_write_eld(struct drm_connector *connector,
struct drm_i915_private *dev_priv = connector->dev->dev_private;
uint8_t *eld = connector->eld;
uint32_t eldv;
- uint32_t i;
- int len;
+ uint32_t tmp;
+ int len, i;
int hdmiw_hdmiedid;
int aud_config;
int aud_cntl_st;
int aud_cntrl_st2;
- int pipe = to_intel_crtc(crtc)->pipe;
+ enum pipe pipe = to_intel_crtc(crtc)->pipe;
+ enum port port;
if (HAS_PCH_IBX(connector->dev)) {
hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
@@ -259,22 +258,22 @@ static void ironlake_write_eld(struct drm_connector *connector,
intel_encoder = intel_attached_encoder(connector);
intel_dig_port = enc_to_dig_port(&intel_encoder->base);
- i = intel_dig_port->port;
+ port = intel_dig_port->port;
} else {
- i = I915_READ(aud_cntl_st);
- i = (i >> 29) & DIP_PORT_SEL_MASK;
+ tmp = I915_READ(aud_cntl_st);
+ port = (tmp >> 29) & DIP_PORT_SEL_MASK;
/* DIP_Port_Select, 0x1 = PortB */
}
- if (!i) {
+ if (!port) {
DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
/* operate blindly on all ports */
eldv = IBX_ELD_VALIDB;
eldv |= IBX_ELD_VALIDB << 4;
eldv |= IBX_ELD_VALIDB << 8;
} else {
- DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
- eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
+ DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(port));
+ eldv = IBX_ELD_VALIDB << ((port - 1) * 4);
}
if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
@@ -291,25 +290,25 @@ static void ironlake_write_eld(struct drm_connector *connector,
hdmiw_hdmiedid))
return;
- i = I915_READ(aud_cntrl_st2);
- i &= ~eldv;
- I915_WRITE(aud_cntrl_st2, i);
+ tmp = I915_READ(aud_cntrl_st2);
+ tmp &= ~eldv;
+ I915_WRITE(aud_cntrl_st2, tmp);
if (!eld[0])
return;
- i = I915_READ(aud_cntl_st);
- i &= ~IBX_ELD_ADDRESS;
- I915_WRITE(aud_cntl_st, i);
+ tmp = I915_READ(aud_cntl_st);
+ tmp &= ~IBX_ELD_ADDRESS;
+ I915_WRITE(aud_cntl_st, tmp);
- len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
+ len = min_t(int, eld[2], 21); /* 84 bytes of hw ELD buffer */
DRM_DEBUG_DRIVER("ELD size %d\n", len);
for (i = 0; i < len; i++)
I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
- i = I915_READ(aud_cntrl_st2);
- i |= eldv;
- I915_WRITE(aud_cntrl_st2, i);
+ tmp = I915_READ(aud_cntrl_st2);
+ tmp |= eldv;
+ I915_WRITE(aud_cntrl_st2, tmp);
}
void intel_write_eld(struct drm_encoder *encoder,
--
1.9.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 04/18] drm/i915: pass intel_encoder to intel_write_eld
2014-10-03 12:43 [PATCH 00/18] drm/i915: hdmi/dp audio rework Jani Nikula
` (2 preceding siblings ...)
2014-10-03 12:43 ` [PATCH 03/18] drm/i915/audio: beat some sense into the variable types and names Jani Nikula
@ 2014-10-03 12:43 ` Jani Nikula
2014-10-03 12:43 ` [PATCH 05/18] drm/i915/audio: pass intel_encoder on to platform specific ELD functions Jani Nikula
` (13 subsequent siblings)
17 siblings, 0 replies; 20+ messages in thread
From: Jani Nikula @ 2014-10-03 12:43 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, shuang.he
Everything else can be derived from that. No functional changes.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/intel_audio.c | 9 +++++----
drivers/gpu/drm/i915/intel_ddi.c | 2 +-
drivers/gpu/drm/i915/intel_dp.c | 2 +-
drivers/gpu/drm/i915/intel_drv.h | 3 +--
drivers/gpu/drm/i915/intel_hdmi.c | 2 +-
5 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_audio.c b/drivers/gpu/drm/i915/intel_audio.c
index 0690a948a6d3..af96b3992c21 100644
--- a/drivers/gpu/drm/i915/intel_audio.c
+++ b/drivers/gpu/drm/i915/intel_audio.c
@@ -311,10 +311,11 @@ static void ironlake_write_eld(struct drm_connector *connector,
I915_WRITE(aud_cntrl_st2, tmp);
}
-void intel_write_eld(struct drm_encoder *encoder,
- struct drm_display_mode *mode)
+void intel_write_eld(struct intel_encoder *intel_encoder)
{
- struct drm_crtc *crtc = encoder->crtc;
+ struct drm_encoder *encoder = &intel_encoder->base;
+ struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
+ struct drm_display_mode *mode = &crtc->config.adjusted_mode;
struct drm_connector *connector;
struct drm_device *dev = encoder->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
@@ -332,7 +333,7 @@ void intel_write_eld(struct drm_encoder *encoder,
connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
if (dev_priv->display.write_eld)
- dev_priv->display.write_eld(connector, crtc, mode);
+ dev_priv->display.write_eld(connector, encoder->crtc, mode);
}
/* Set up chip specific audio functions */
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index a151de7d13cd..026569464bc4 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1126,7 +1126,7 @@ static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
/* write eld */
DRM_DEBUG_DRIVER("DDI audio: write eld information\n");
- intel_write_eld(encoder, &crtc->config.adjusted_mode);
+ intel_write_eld(intel_encoder);
}
if (type == INTEL_OUTPUT_EDP) {
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 64c8e047891d..b474a29d00d5 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1250,7 +1250,7 @@ static void intel_dp_prepare(struct intel_encoder *encoder)
DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
pipe_name(crtc->pipe));
intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
- intel_write_eld(&encoder->base, adjusted_mode);
+ intel_write_eld(encoder);
}
/* Split out the IBX/CPU vs CPT settings */
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index e14c88f9f4d2..3fcabe57b534 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -841,8 +841,7 @@ void intel_fb_obj_flush(struct drm_i915_gem_object *obj, bool retire);
/* intel_audio.c */
void intel_init_audio(struct drm_device *dev);
-void intel_write_eld(struct drm_encoder *encoder,
- struct drm_display_mode *mode);
+void intel_write_eld(struct intel_encoder *encoder);
/* intel_display.c */
const char *intel_output_name(int output);
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index 8b5f3aa027f3..07b5ebd65d41 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -666,7 +666,7 @@ static void intel_hdmi_prepare(struct intel_encoder *encoder)
DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
pipe_name(crtc->pipe));
hdmi_val |= SDVO_AUDIO_ENABLE;
- intel_write_eld(&encoder->base, adjusted_mode);
+ intel_write_eld(encoder);
}
if (HAS_PCH_CPT(dev))
--
1.9.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 05/18] drm/i915/audio: pass intel_encoder on to platform specific ELD functions
2014-10-03 12:43 [PATCH 00/18] drm/i915: hdmi/dp audio rework Jani Nikula
` (3 preceding siblings ...)
2014-10-03 12:43 ` [PATCH 04/18] drm/i915: pass intel_encoder to intel_write_eld Jani Nikula
@ 2014-10-03 12:43 ` Jani Nikula
2014-10-03 12:43 ` [PATCH 06/18] drm/i915/audio: set ELD Conn_Type at one place Jani Nikula
` (12 subsequent siblings)
17 siblings, 0 replies; 20+ messages in thread
From: Jani Nikula @ 2014-10-03 12:43 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, shuang.he
This will simplify things later on. No functional changes.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 4 ++--
drivers/gpu/drm/i915/intel_audio.c | 14 +++++++-------
2 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index bf4cb992869b..1cce66a02853 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -434,6 +434,7 @@ struct drm_i915_error_state {
};
struct intel_connector;
+struct intel_encoder;
struct intel_crtc_config;
struct intel_plane_config;
struct intel_crtc;
@@ -483,7 +484,7 @@ struct drm_i915_display_funcs {
void (*crtc_disable)(struct drm_crtc *crtc);
void (*off)(struct drm_crtc *crtc);
void (*write_eld)(struct drm_connector *connector,
- struct drm_crtc *crtc,
+ struct intel_encoder *encoder,
struct drm_display_mode *mode);
void (*fdi_link_train)(struct drm_crtc *crtc);
void (*init_clock_gating)(struct drm_device *dev);
@@ -2784,7 +2785,6 @@ static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
extern void intel_i2c_reset(struct drm_device *dev);
/* intel_opregion.c */
-struct intel_encoder;
#ifdef CONFIG_ACPI
extern int intel_opregion_setup(struct drm_device *dev);
extern void intel_opregion_init(struct drm_device *dev);
diff --git a/drivers/gpu/drm/i915/intel_audio.c b/drivers/gpu/drm/i915/intel_audio.c
index af96b3992c21..763481d1c510 100644
--- a/drivers/gpu/drm/i915/intel_audio.c
+++ b/drivers/gpu/drm/i915/intel_audio.c
@@ -97,7 +97,7 @@ static bool intel_eld_uptodate(struct drm_connector *connector,
}
static void g4x_write_eld(struct drm_connector *connector,
- struct drm_crtc *crtc,
+ struct intel_encoder *encoder,
struct drm_display_mode *mode)
{
struct drm_i915_private *dev_priv = connector->dev->dev_private;
@@ -137,10 +137,11 @@ static void g4x_write_eld(struct drm_connector *connector,
}
static void haswell_write_eld(struct drm_connector *connector,
- struct drm_crtc *crtc,
+ struct intel_encoder *encoder,
struct drm_display_mode *mode)
{
struct drm_i915_private *dev_priv = connector->dev->dev_private;
+ struct drm_crtc *crtc = encoder->base.crtc;
uint8_t *eld = connector->eld;
uint32_t eldv;
uint32_t tmp;
@@ -218,10 +219,11 @@ static void haswell_write_eld(struct drm_connector *connector,
}
static void ironlake_write_eld(struct drm_connector *connector,
- struct drm_crtc *crtc,
+ struct intel_encoder *encoder,
struct drm_display_mode *mode)
{
struct drm_i915_private *dev_priv = connector->dev->dev_private;
+ struct drm_crtc *crtc = encoder->base.crtc;
uint8_t *eld = connector->eld;
uint32_t eldv;
uint32_t tmp;
@@ -253,11 +255,9 @@ static void ironlake_write_eld(struct drm_connector *connector,
DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
if (IS_VALLEYVIEW(connector->dev)) {
- struct intel_encoder *intel_encoder;
struct intel_digital_port *intel_dig_port;
- intel_encoder = intel_attached_encoder(connector);
- intel_dig_port = enc_to_dig_port(&intel_encoder->base);
+ intel_dig_port = enc_to_dig_port(&encoder->base);
port = intel_dig_port->port;
} else {
tmp = I915_READ(aud_cntl_st);
@@ -333,7 +333,7 @@ void intel_write_eld(struct intel_encoder *intel_encoder)
connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
if (dev_priv->display.write_eld)
- dev_priv->display.write_eld(connector, encoder->crtc, mode);
+ dev_priv->display.write_eld(connector, intel_encoder, mode);
}
/* Set up chip specific audio functions */
--
1.9.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 06/18] drm/i915/audio: set ELD Conn_Type at one place
2014-10-03 12:43 [PATCH 00/18] drm/i915: hdmi/dp audio rework Jani Nikula
` (4 preceding siblings ...)
2014-10-03 12:43 ` [PATCH 05/18] drm/i915/audio: pass intel_encoder on to platform specific ELD functions Jani Nikula
@ 2014-10-03 12:43 ` Jani Nikula
2014-10-03 12:43 ` [PATCH 07/18] drm/i915/ddi: write ELD where it's supposed to be done Jani Nikula
` (11 subsequent siblings)
17 siblings, 0 replies; 20+ messages in thread
From: Jani Nikula @ 2014-10-03 12:43 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, shuang.he
Keep the driver modifications to ELD together. This also sets the
Conn_Type for G4X DP which wasn't done before.
Clean up the debugs while at it; this is all obvious from the connector
name.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/intel_audio.c | 19 +++++++++----------
1 file changed, 9 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_audio.c b/drivers/gpu/drm/i915/intel_audio.c
index 763481d1c510..366f058889b3 100644
--- a/drivers/gpu/drm/i915/intel_audio.c
+++ b/drivers/gpu/drm/i915/intel_audio.c
@@ -181,13 +181,10 @@ static void haswell_write_eld(struct drm_connector *connector,
eldv = AUDIO_ELD_VALID_A << (pipe * 4);
- if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
- DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
- eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
+ if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
- } else {
+ else
I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
- }
if (intel_eld_uptodate(connector,
aud_cntrl_st2, eldv,
@@ -276,13 +273,10 @@ static void ironlake_write_eld(struct drm_connector *connector,
eldv = IBX_ELD_VALIDB << ((port - 1) * 4);
}
- if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
- DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
- eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
+ if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
- } else {
+ else
I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
- }
if (intel_eld_uptodate(connector,
aud_cntrl_st2, eldv,
@@ -330,6 +324,11 @@ void intel_write_eld(struct intel_encoder *intel_encoder)
connector->encoder->base.id,
connector->encoder->name);
+ /* ELD Conn_Type */
+ connector->eld[5] &= (3 << 2);
+ if (intel_pipe_has_type(encoder->crtc, INTEL_OUTPUT_DISPLAYPORT))
+ connector->eld[5] |= (1 << 2);
+
connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
if (dev_priv->display.write_eld)
--
1.9.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 07/18] drm/i915/ddi: write ELD where it's supposed to be done
2014-10-03 12:43 [PATCH 00/18] drm/i915: hdmi/dp audio rework Jani Nikula
` (5 preceding siblings ...)
2014-10-03 12:43 ` [PATCH 06/18] drm/i915/audio: set ELD Conn_Type at one place Jani Nikula
@ 2014-10-03 12:43 ` Jani Nikula
2014-10-03 12:43 ` [PATCH 08/18] drm/i915: introduce intel_audio_codec_{enable, disable} Jani Nikula
` (10 subsequent siblings)
17 siblings, 0 replies; 20+ messages in thread
From: Jani Nikula @ 2014-10-03 12:43 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, shuang.he
The audio programming sequence states that the ELD must be written and
enabled after the pipe is ready. Indeed, this should clarify the
situation with
commit c79057922ed6c2c6df1214e6ab4414fea1b23db2
Author: Daniel Vetter <daniel.vetter@ffwll.ch>
Date: Wed Apr 16 16:56:09 2014 +0200
drm/i915: Remove vblank wait from haswell_write_eld
and Ville's review of it [1].
Moreover, we should not touch the relevant registers before we get the
audio power domain.
[1] http://mid.gmane.org/20140416155309.GK18465@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/intel_audio.c | 2 --
drivers/gpu/drm/i915/intel_ddi.c | 11 ++---------
2 files changed, 2 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_audio.c b/drivers/gpu/drm/i915/intel_audio.c
index 366f058889b3..7baac1b8d75a 100644
--- a/drivers/gpu/drm/i915/intel_audio.c
+++ b/drivers/gpu/drm/i915/intel_audio.c
@@ -160,8 +160,6 @@ static void haswell_write_eld(struct drm_connector *connector,
I915_WRITE(aud_cntrl_st2, tmp);
POSTING_READ(aud_cntrl_st2);
- assert_pipe_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
-
/* Set ELD valid state */
tmp = I915_READ(aud_cntrl_st2);
DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 026569464bc4..e6d2aee36759 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1120,15 +1120,6 @@ static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
enum port port = intel_ddi_get_encoder_port(intel_encoder);
int type = intel_encoder->type;
- if (crtc->config.has_audio) {
- DRM_DEBUG_DRIVER("Audio on pipe %c on DDI\n",
- pipe_name(crtc->pipe));
-
- /* write eld */
- DRM_DEBUG_DRIVER("DDI audio: write eld information\n");
- intel_write_eld(intel_encoder);
- }
-
if (type == INTEL_OUTPUT_EDP) {
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
intel_edp_panel_on(intel_dp);
@@ -1225,6 +1216,8 @@ static void intel_enable_ddi(struct intel_encoder *intel_encoder)
if (intel_crtc->config.has_audio) {
intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
+ intel_write_eld(intel_encoder);
+
tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
tmp |= ((AUDIO_OUTPUT_ENABLE_A | AUDIO_ELD_VALID_A) << (pipe * 4));
I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
--
1.9.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 08/18] drm/i915: introduce intel_audio_codec_{enable, disable}
2014-10-03 12:43 [PATCH 00/18] drm/i915: hdmi/dp audio rework Jani Nikula
` (6 preceding siblings ...)
2014-10-03 12:43 ` [PATCH 07/18] drm/i915/ddi: write ELD where it's supposed to be done Jani Nikula
@ 2014-10-03 12:43 ` Jani Nikula
2014-10-03 12:43 ` [PATCH 09/18] drm/i915/audio: remove misleading checks for !eld[0] Jani Nikula
` (9 subsequent siblings)
17 siblings, 0 replies; 20+ messages in thread
From: Jani Nikula @ 2014-10-03 12:43 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, shuang.he
Introduce functions to enable/disable the audio codec, incorporating the
ELD setup within enable. The disable is initially limited to HSW,
covering exactly what was done previously.
The only functional difference is that ELD valid is no longer set if
there is no connector with ELD, which should be the right thing to do
anyway. Otherwise the sequence remains the same, with warts and all, in
preparation for applying more sanity.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 7 ++--
drivers/gpu/drm/i915/intel_audio.c | 69 +++++++++++++++++++++++++++-----------
drivers/gpu/drm/i915/intel_ddi.c | 17 ++--------
drivers/gpu/drm/i915/intel_dp.c | 2 +-
drivers/gpu/drm/i915/intel_drv.h | 3 +-
drivers/gpu/drm/i915/intel_hdmi.c | 2 +-
6 files changed, 59 insertions(+), 41 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 1cce66a02853..091546b1837c 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -483,9 +483,10 @@ struct drm_i915_display_funcs {
void (*crtc_enable)(struct drm_crtc *crtc);
void (*crtc_disable)(struct drm_crtc *crtc);
void (*off)(struct drm_crtc *crtc);
- void (*write_eld)(struct drm_connector *connector,
- struct intel_encoder *encoder,
- struct drm_display_mode *mode);
+ void (*audio_codec_enable)(struct drm_connector *connector,
+ struct intel_encoder *encoder,
+ struct drm_display_mode *mode);
+ void (*audio_codec_disable)(struct intel_encoder *encoder);
void (*fdi_link_train)(struct drm_crtc *crtc);
void (*init_clock_gating)(struct drm_device *dev);
int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
diff --git a/drivers/gpu/drm/i915/intel_audio.c b/drivers/gpu/drm/i915/intel_audio.c
index 7baac1b8d75a..2131401c0ae9 100644
--- a/drivers/gpu/drm/i915/intel_audio.c
+++ b/drivers/gpu/drm/i915/intel_audio.c
@@ -96,9 +96,9 @@ static bool intel_eld_uptodate(struct drm_connector *connector,
return true;
}
-static void g4x_write_eld(struct drm_connector *connector,
- struct intel_encoder *encoder,
- struct drm_display_mode *mode)
+static void g4x_audio_codec_enable(struct drm_connector *connector,
+ struct intel_encoder *encoder,
+ struct drm_display_mode *mode)
{
struct drm_i915_private *dev_priv = connector->dev->dev_private;
uint8_t *eld = connector->eld;
@@ -136,9 +136,22 @@ static void g4x_write_eld(struct drm_connector *connector,
I915_WRITE(G4X_AUD_CNTL_ST, tmp);
}
-static void haswell_write_eld(struct drm_connector *connector,
- struct intel_encoder *encoder,
- struct drm_display_mode *mode)
+static void hsw_audio_codec_disable(struct intel_encoder *encoder)
+{
+ struct drm_device *dev = encoder->base.dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_crtc *crtc = encoder->base.crtc;
+ enum pipe pipe = to_intel_crtc(crtc)->pipe;
+ uint32_t tmp;
+
+ tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
+ tmp &= ~((AUDIO_OUTPUT_ENABLE_A | AUDIO_ELD_VALID_A) << (pipe * 4));
+ I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
+}
+
+static void hsw_audio_codec_enable(struct drm_connector *connector,
+ struct intel_encoder *encoder,
+ struct drm_display_mode *mode)
{
struct drm_i915_private *dev_priv = connector->dev->dev_private;
struct drm_crtc *crtc = encoder->base.crtc;
@@ -211,11 +224,16 @@ static void haswell_write_eld(struct drm_connector *connector,
tmp = I915_READ(aud_cntrl_st2);
tmp |= eldv;
I915_WRITE(aud_cntrl_st2, tmp);
+
+ /* XXX: Transitional */
+ tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
+ tmp |= ((AUDIO_OUTPUT_ENABLE_A | AUDIO_ELD_VALID_A) << (pipe * 4));
+ I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
}
-static void ironlake_write_eld(struct drm_connector *connector,
- struct intel_encoder *encoder,
- struct drm_display_mode *mode)
+static void ilk_audio_codec_enable(struct drm_connector *connector,
+ struct intel_encoder *encoder,
+ struct drm_display_mode *mode)
{
struct drm_i915_private *dev_priv = connector->dev->dev_private;
struct drm_crtc *crtc = encoder->base.crtc;
@@ -303,7 +321,7 @@ static void ironlake_write_eld(struct drm_connector *connector,
I915_WRITE(aud_cntrl_st2, tmp);
}
-void intel_write_eld(struct intel_encoder *intel_encoder)
+void intel_audio_codec_enable(struct intel_encoder *intel_encoder)
{
struct drm_encoder *encoder = &intel_encoder->base;
struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
@@ -329,8 +347,17 @@ void intel_write_eld(struct intel_encoder *intel_encoder)
connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
- if (dev_priv->display.write_eld)
- dev_priv->display.write_eld(connector, intel_encoder, mode);
+ if (dev_priv->display.audio_codec_enable)
+ dev_priv->display.audio_codec_enable(connector, intel_encoder, mode);
+}
+
+void intel_audio_codec_disable(struct intel_encoder *encoder)
+{
+ struct drm_device *dev = encoder->base.dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+
+ if (dev_priv->display.audio_codec_disable)
+ dev_priv->display.audio_codec_disable(encoder);
}
/* Set up chip specific audio functions */
@@ -338,12 +365,14 @@ void intel_init_audio(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
- if (IS_G4X(dev))
- dev_priv->display.write_eld = g4x_write_eld;
- else if (IS_VALLEYVIEW(dev))
- dev_priv->display.write_eld = ironlake_write_eld;
- else if (IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8)
- dev_priv->display.write_eld = haswell_write_eld;
- else if (HAS_PCH_SPLIT(dev))
- dev_priv->display.write_eld = ironlake_write_eld;
+ if (IS_G4X(dev)) {
+ dev_priv->display.audio_codec_enable = g4x_audio_codec_enable;
+ } else if (IS_VALLEYVIEW(dev)) {
+ dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;
+ } else if (IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8) {
+ dev_priv->display.audio_codec_enable = hsw_audio_codec_enable;
+ dev_priv->display.audio_codec_disable = hsw_audio_codec_disable;
+ } else if (HAS_PCH_SPLIT(dev)) {
+ dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;
+ }
}
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index e6d2aee36759..ba3dccc055d4 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1186,12 +1186,10 @@ static void intel_enable_ddi(struct intel_encoder *intel_encoder)
struct drm_encoder *encoder = &intel_encoder->base;
struct drm_crtc *crtc = encoder->crtc;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
- int pipe = intel_crtc->pipe;
struct drm_device *dev = encoder->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
enum port port = intel_ddi_get_encoder_port(intel_encoder);
int type = intel_encoder->type;
- uint32_t tmp;
if (type == INTEL_OUTPUT_HDMI) {
struct intel_digital_port *intel_dig_port =
@@ -1216,11 +1214,7 @@ static void intel_enable_ddi(struct intel_encoder *intel_encoder)
if (intel_crtc->config.has_audio) {
intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
- intel_write_eld(intel_encoder);
-
- tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
- tmp |= ((AUDIO_OUTPUT_ENABLE_A | AUDIO_ELD_VALID_A) << (pipe * 4));
- I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
+ intel_audio_codec_enable(intel_encoder);
}
}
@@ -1229,19 +1223,12 @@ static void intel_disable_ddi(struct intel_encoder *intel_encoder)
struct drm_encoder *encoder = &intel_encoder->base;
struct drm_crtc *crtc = encoder->crtc;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
- int pipe = intel_crtc->pipe;
int type = intel_encoder->type;
struct drm_device *dev = encoder->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
- uint32_t tmp;
- /* We can't touch HSW_AUD_PIN_ELD_CP_VLD uncionditionally because this
- * register is part of the power well on Haswell. */
if (intel_crtc->config.has_audio) {
- tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
- tmp &= ~((AUDIO_OUTPUT_ENABLE_A | AUDIO_ELD_VALID_A) <<
- (pipe * 4));
- I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
+ intel_audio_codec_disable(intel_encoder);
intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
}
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index b474a29d00d5..80e94def24eb 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1250,7 +1250,7 @@ static void intel_dp_prepare(struct intel_encoder *encoder)
DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
pipe_name(crtc->pipe));
intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
- intel_write_eld(encoder);
+ intel_audio_codec_enable(encoder);
}
/* Split out the IBX/CPU vs CPT settings */
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 3fcabe57b534..b3b608b9b72e 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -841,7 +841,8 @@ void intel_fb_obj_flush(struct drm_i915_gem_object *obj, bool retire);
/* intel_audio.c */
void intel_init_audio(struct drm_device *dev);
-void intel_write_eld(struct intel_encoder *encoder);
+void intel_audio_codec_enable(struct intel_encoder *encoder);
+void intel_audio_codec_disable(struct intel_encoder *encoder);
/* intel_display.c */
const char *intel_output_name(int output);
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index 07b5ebd65d41..f29026a1157d 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -666,7 +666,7 @@ static void intel_hdmi_prepare(struct intel_encoder *encoder)
DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
pipe_name(crtc->pipe));
hdmi_val |= SDVO_AUDIO_ENABLE;
- intel_write_eld(encoder);
+ intel_audio_codec_enable(encoder);
}
if (HAS_PCH_CPT(dev))
--
1.9.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 09/18] drm/i915/audio: remove misleading checks for !eld[0]
2014-10-03 12:43 [PATCH 00/18] drm/i915: hdmi/dp audio rework Jani Nikula
` (7 preceding siblings ...)
2014-10-03 12:43 ` [PATCH 08/18] drm/i915: introduce intel_audio_codec_{enable, disable} Jani Nikula
@ 2014-10-03 12:43 ` Jani Nikula
2014-10-03 12:43 ` [PATCH 10/18] drm/i915: clean up and clarify audio related register defines Jani Nikula
` (8 subsequent siblings)
17 siblings, 0 replies; 20+ messages in thread
From: Jani Nikula @ 2014-10-03 12:43 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, shuang.he
We'll never end up in the hooks with eld[0] unset, as that's checked by
drm_select_eld().
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/intel_audio.c | 12 ------------
1 file changed, 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_audio.c b/drivers/gpu/drm/i915/intel_audio.c
index 2131401c0ae9..c845d155e93e 100644
--- a/drivers/gpu/drm/i915/intel_audio.c
+++ b/drivers/gpu/drm/i915/intel_audio.c
@@ -79,9 +79,6 @@ static bool intel_eld_uptodate(struct drm_connector *connector,
tmp = I915_READ(reg_eldv);
tmp &= bits_eldv;
- if (!eld[0])
- return !tmp;
-
if (!tmp)
return false;
@@ -123,9 +120,6 @@ static void g4x_audio_codec_enable(struct drm_connector *connector,
len = (tmp >> 9) & 0x1f; /* ELD buffer size */
I915_WRITE(G4X_AUD_CNTL_ST, tmp);
- if (!eld[0])
- return;
-
len = min_t(int, eld[2], len);
DRM_DEBUG_DRIVER("ELD size %d\n", len);
for (i = 0; i < len; i++)
@@ -207,9 +201,6 @@ static void hsw_audio_codec_enable(struct drm_connector *connector,
tmp &= ~eldv;
I915_WRITE(aud_cntrl_st2, tmp);
- if (!eld[0])
- return;
-
tmp = I915_READ(aud_cntl_st);
tmp &= ~IBX_ELD_ADDRESS;
I915_WRITE(aud_cntl_st, tmp);
@@ -304,9 +295,6 @@ static void ilk_audio_codec_enable(struct drm_connector *connector,
tmp &= ~eldv;
I915_WRITE(aud_cntrl_st2, tmp);
- if (!eld[0])
- return;
-
tmp = I915_READ(aud_cntl_st);
tmp &= ~IBX_ELD_ADDRESS;
I915_WRITE(aud_cntl_st, tmp);
--
1.9.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 10/18] drm/i915: clean up and clarify audio related register defines
2014-10-03 12:43 [PATCH 00/18] drm/i915: hdmi/dp audio rework Jani Nikula
` (8 preceding siblings ...)
2014-10-03 12:43 ` [PATCH 09/18] drm/i915/audio: remove misleading checks for !eld[0] Jani Nikula
@ 2014-10-03 12:43 ` Jani Nikula
2014-10-03 12:43 ` [PATCH 11/18] drm/i915: rewrite hsw/bdw audio codec enable/disable sequences Jani Nikula
` (7 subsequent siblings)
17 siblings, 0 replies; 20+ messages in thread
From: Jani Nikula @ 2014-10-03 12:43 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, shuang.he
Make audio related register defines conform to existing style: Add _MASK
where relevant, indent the defines for register contents, don't indent
the defines for register addresses, prefix pipe specific register
address defines with underscores, drop self explanatory comments.
No functional changes.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 165 +++++++++++++++++++------------------
drivers/gpu/drm/i915/intel_audio.c | 12 +--
2 files changed, 89 insertions(+), 88 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a56d9a7e7e0e..b914e7932a76 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5950,57 +5950,58 @@ enum punit_power_well {
#define GEN8_CENTROID_PIXEL_OPT_DIS (1<<8)
#define GEN8_SAMPLER_POWER_BYPASS_DIS (1<<1)
+/* Audio */
#define G4X_AUD_VID_DID (dev_priv->info.display_mmio_offset + 0x62020)
-#define INTEL_AUDIO_DEVCL 0x808629FB
-#define INTEL_AUDIO_DEVBLC 0x80862801
-#define INTEL_AUDIO_DEVCTG 0x80862802
+#define INTEL_AUDIO_DEVCL 0x808629FB
+#define INTEL_AUDIO_DEVBLC 0x80862801
+#define INTEL_AUDIO_DEVCTG 0x80862802
#define G4X_AUD_CNTL_ST 0x620B4
-#define G4X_ELDV_DEVCL_DEVBLC (1 << 13)
-#define G4X_ELDV_DEVCTG (1 << 14)
-#define G4X_ELD_ADDR (0xf << 5)
-#define G4X_ELD_ACK (1 << 4)
+#define G4X_ELDV_DEVCL_DEVBLC (1 << 13)
+#define G4X_ELDV_DEVCTG (1 << 14)
+#define G4X_ELD_ADDR_MASK (0xf << 5)
+#define G4X_ELD_ACK (1 << 4)
#define G4X_HDMIW_HDMIEDID 0x6210C
-#define IBX_HDMIW_HDMIEDID_A 0xE2050
-#define IBX_HDMIW_HDMIEDID_B 0xE2150
+#define _IBX_HDMIW_HDMIEDID_A 0xE2050
+#define _IBX_HDMIW_HDMIEDID_B 0xE2150
#define IBX_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \
- IBX_HDMIW_HDMIEDID_A, \
- IBX_HDMIW_HDMIEDID_B)
-#define IBX_AUD_CNTL_ST_A 0xE20B4
-#define IBX_AUD_CNTL_ST_B 0xE21B4
+ _IBX_HDMIW_HDMIEDID_A, \
+ _IBX_HDMIW_HDMIEDID_B)
+#define _IBX_AUD_CNTL_ST_A 0xE20B4
+#define _IBX_AUD_CNTL_ST_B 0xE21B4
#define IBX_AUD_CNTL_ST(pipe) _PIPE(pipe, \
- IBX_AUD_CNTL_ST_A, \
- IBX_AUD_CNTL_ST_B)
-#define IBX_ELD_BUFFER_SIZE (0x1f << 10)
-#define IBX_ELD_ADDRESS (0x1f << 5)
-#define IBX_ELD_ACK (1 << 4)
+ _IBX_AUD_CNTL_ST_A, \
+ _IBX_AUD_CNTL_ST_B)
+#define IBX_ELD_BUFFER_SIZE_MASK (0x1f << 10)
+#define IBX_ELD_ADDRESS_MASK (0x1f << 5)
+#define IBX_ELD_ACK (1 << 4)
#define IBX_AUD_CNTL_ST2 0xE20C0
-#define IBX_ELD_VALIDB (1 << 0)
-#define IBX_CP_READYB (1 << 1)
+#define IBX_ELD_VALIDB (1 << 0)
+#define IBX_CP_READYB (1 << 1)
-#define CPT_HDMIW_HDMIEDID_A 0xE5050
-#define CPT_HDMIW_HDMIEDID_B 0xE5150
+#define _CPT_HDMIW_HDMIEDID_A 0xE5050
+#define _CPT_HDMIW_HDMIEDID_B 0xE5150
#define CPT_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \
- CPT_HDMIW_HDMIEDID_A, \
- CPT_HDMIW_HDMIEDID_B)
-#define CPT_AUD_CNTL_ST_A 0xE50B4
-#define CPT_AUD_CNTL_ST_B 0xE51B4
+ _CPT_HDMIW_HDMIEDID_A, \
+ _CPT_HDMIW_HDMIEDID_B)
+#define _CPT_AUD_CNTL_ST_A 0xE50B4
+#define _CPT_AUD_CNTL_ST_B 0xE51B4
#define CPT_AUD_CNTL_ST(pipe) _PIPE(pipe, \
- CPT_AUD_CNTL_ST_A, \
- CPT_AUD_CNTL_ST_B)
+ _CPT_AUD_CNTL_ST_A, \
+ _CPT_AUD_CNTL_ST_B)
#define CPT_AUD_CNTRL_ST2 0xE50C0
-#define VLV_HDMIW_HDMIEDID_A (VLV_DISPLAY_BASE + 0x62050)
-#define VLV_HDMIW_HDMIEDID_B (VLV_DISPLAY_BASE + 0x62150)
+#define _VLV_HDMIW_HDMIEDID_A (VLV_DISPLAY_BASE + 0x62050)
+#define _VLV_HDMIW_HDMIEDID_B (VLV_DISPLAY_BASE + 0x62150)
#define VLV_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \
- VLV_HDMIW_HDMIEDID_A, \
- VLV_HDMIW_HDMIEDID_B)
-#define VLV_AUD_CNTL_ST_A (VLV_DISPLAY_BASE + 0x620B4)
-#define VLV_AUD_CNTL_ST_B (VLV_DISPLAY_BASE + 0x621B4)
+ _VLV_HDMIW_HDMIEDID_A, \
+ _VLV_HDMIW_HDMIEDID_B)
+#define _VLV_AUD_CNTL_ST_A (VLV_DISPLAY_BASE + 0x620B4)
+#define _VLV_AUD_CNTL_ST_B (VLV_DISPLAY_BASE + 0x621B4)
#define VLV_AUD_CNTL_ST(pipe) _PIPE(pipe, \
- VLV_AUD_CNTL_ST_A, \
- VLV_AUD_CNTL_ST_B)
+ _VLV_AUD_CNTL_ST_A, \
+ _VLV_AUD_CNTL_ST_B)
#define VLV_AUD_CNTL_ST2 (VLV_DISPLAY_BASE + 0x620C0)
/* These are the 4 32-bit write offset registers for each stream
@@ -6009,28 +6010,28 @@ enum punit_power_well {
*/
#define GEN7_SO_WRITE_OFFSET(n) (0x5280 + (n) * 4)
-#define IBX_AUD_CONFIG_A 0xe2000
-#define IBX_AUD_CONFIG_B 0xe2100
+#define _IBX_AUD_CONFIG_A 0xe2000
+#define _IBX_AUD_CONFIG_B 0xe2100
#define IBX_AUD_CFG(pipe) _PIPE(pipe, \
- IBX_AUD_CONFIG_A, \
- IBX_AUD_CONFIG_B)
-#define CPT_AUD_CONFIG_A 0xe5000
-#define CPT_AUD_CONFIG_B 0xe5100
+ _IBX_AUD_CONFIG_A, \
+ _IBX_AUD_CONFIG_B)
+#define _CPT_AUD_CONFIG_A 0xe5000
+#define _CPT_AUD_CONFIG_B 0xe5100
#define CPT_AUD_CFG(pipe) _PIPE(pipe, \
- CPT_AUD_CONFIG_A, \
- CPT_AUD_CONFIG_B)
-#define VLV_AUD_CONFIG_A (VLV_DISPLAY_BASE + 0x62000)
-#define VLV_AUD_CONFIG_B (VLV_DISPLAY_BASE + 0x62100)
+ _CPT_AUD_CONFIG_A, \
+ _CPT_AUD_CONFIG_B)
+#define _VLV_AUD_CONFIG_A (VLV_DISPLAY_BASE + 0x62000)
+#define _VLV_AUD_CONFIG_B (VLV_DISPLAY_BASE + 0x62100)
#define VLV_AUD_CFG(pipe) _PIPE(pipe, \
- VLV_AUD_CONFIG_A, \
- VLV_AUD_CONFIG_B)
+ _VLV_AUD_CONFIG_A, \
+ _VLV_AUD_CONFIG_B)
#define AUD_CONFIG_N_VALUE_INDEX (1 << 29)
#define AUD_CONFIG_N_PROG_ENABLE (1 << 28)
#define AUD_CONFIG_UPPER_N_SHIFT 20
-#define AUD_CONFIG_UPPER_N_VALUE (0xff << 20)
+#define AUD_CONFIG_UPPER_N_MASK (0xff << 20)
#define AUD_CONFIG_LOWER_N_SHIFT 4
-#define AUD_CONFIG_LOWER_N_VALUE (0xfff << 4)
+#define AUD_CONFIG_LOWER_N_MASK (0xfff << 4)
#define AUD_CONFIG_PIXEL_CLOCK_HDMI_SHIFT 16
#define AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK (0xf << 16)
#define AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 (0 << 16)
@@ -6046,40 +6047,40 @@ enum punit_power_well {
#define AUD_CONFIG_DISABLE_NCTS (1 << 3)
/* HSW Audio */
-#define HSW_AUD_CONFIG_A 0x65000 /* Audio Configuration Transcoder A */
-#define HSW_AUD_CONFIG_B 0x65100 /* Audio Configuration Transcoder B */
-#define HSW_AUD_CFG(pipe) _PIPE(pipe, \
- HSW_AUD_CONFIG_A, \
- HSW_AUD_CONFIG_B)
-
-#define HSW_AUD_MISC_CTRL_A 0x65010 /* Audio Misc Control Convert 1 */
-#define HSW_AUD_MISC_CTRL_B 0x65110 /* Audio Misc Control Convert 2 */
-#define HSW_AUD_MISC_CTRL(pipe) _PIPE(pipe, \
- HSW_AUD_MISC_CTRL_A, \
- HSW_AUD_MISC_CTRL_B)
-
-#define HSW_AUD_DIP_ELD_CTRL_ST_A 0x650b4 /* Audio DIP and ELD Control State Transcoder A */
-#define HSW_AUD_DIP_ELD_CTRL_ST_B 0x651b4 /* Audio DIP and ELD Control State Transcoder B */
-#define HSW_AUD_DIP_ELD_CTRL(pipe) _PIPE(pipe, \
- HSW_AUD_DIP_ELD_CTRL_ST_A, \
- HSW_AUD_DIP_ELD_CTRL_ST_B)
+#define _HSW_AUD_CONFIG_A 0x65000
+#define _HSW_AUD_CONFIG_B 0x65100
+#define HSW_AUD_CFG(pipe) _PIPE(pipe, \
+ _HSW_AUD_CONFIG_A, \
+ _HSW_AUD_CONFIG_B)
+
+#define _HSW_AUD_MISC_CTRL_A 0x65010
+#define _HSW_AUD_MISC_CTRL_B 0x65110
+#define HSW_AUD_MISC_CTRL(pipe) _PIPE(pipe, \
+ _HSW_AUD_MISC_CTRL_A, \
+ _HSW_AUD_MISC_CTRL_B)
+
+#define _HSW_AUD_DIP_ELD_CTRL_ST_A 0x650b4
+#define _HSW_AUD_DIP_ELD_CTRL_ST_B 0x651b4
+#define HSW_AUD_DIP_ELD_CTRL(pipe) _PIPE(pipe, \
+ _HSW_AUD_DIP_ELD_CTRL_ST_A, \
+ _HSW_AUD_DIP_ELD_CTRL_ST_B)
/* Audio Digital Converter */
-#define HSW_AUD_DIG_CNVT_1 0x65080 /* Audio Converter 1 */
-#define HSW_AUD_DIG_CNVT_2 0x65180 /* Audio Converter 1 */
-#define AUD_DIG_CNVT(pipe) _PIPE(pipe, \
- HSW_AUD_DIG_CNVT_1, \
- HSW_AUD_DIG_CNVT_2)
-#define DIP_PORT_SEL_MASK 0x3
-
-#define HSW_AUD_EDID_DATA_A 0x65050
-#define HSW_AUD_EDID_DATA_B 0x65150
-#define HSW_AUD_EDID_DATA(pipe) _PIPE(pipe, \
- HSW_AUD_EDID_DATA_A, \
- HSW_AUD_EDID_DATA_B)
-
-#define HSW_AUD_PIPE_CONV_CFG 0x6507c /* Audio pipe and converter configs */
-#define HSW_AUD_PIN_ELD_CP_VLD 0x650c0 /* Audio ELD and CP Ready Status */
+#define _HSW_AUD_DIG_CNVT_1 0x65080
+#define _HSW_AUD_DIG_CNVT_2 0x65180
+#define AUD_DIG_CNVT(pipe) _PIPE(pipe, \
+ _HSW_AUD_DIG_CNVT_1, \
+ _HSW_AUD_DIG_CNVT_2)
+#define DIP_PORT_SEL_MASK 0x3
+
+#define _HSW_AUD_EDID_DATA_A 0x65050
+#define _HSW_AUD_EDID_DATA_B 0x65150
+#define HSW_AUD_EDID_DATA(pipe) _PIPE(pipe, \
+ _HSW_AUD_EDID_DATA_A, \
+ _HSW_AUD_EDID_DATA_B)
+
+#define HSW_AUD_PIPE_CONV_CFG 0x6507c
+#define HSW_AUD_PIN_ELD_CP_VLD 0x650c0
#define AUDIO_INACTIVE_C (1<<11)
#define AUDIO_INACTIVE_B (1<<7)
#define AUDIO_INACTIVE_A (1<<3)
diff --git a/drivers/gpu/drm/i915/intel_audio.c b/drivers/gpu/drm/i915/intel_audio.c
index c845d155e93e..6e4220bdcbbf 100644
--- a/drivers/gpu/drm/i915/intel_audio.c
+++ b/drivers/gpu/drm/i915/intel_audio.c
@@ -111,12 +111,12 @@ static void g4x_audio_codec_enable(struct drm_connector *connector,
if (intel_eld_uptodate(connector,
G4X_AUD_CNTL_ST, eldv,
- G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
+ G4X_AUD_CNTL_ST, G4X_ELD_ADDR_MASK,
G4X_HDMIW_HDMIEDID))
return;
tmp = I915_READ(G4X_AUD_CNTL_ST);
- tmp &= ~(eldv | G4X_ELD_ADDR);
+ tmp &= ~(eldv | G4X_ELD_ADDR_MASK);
len = (tmp >> 9) & 0x1f; /* ELD buffer size */
I915_WRITE(G4X_AUD_CNTL_ST, tmp);
@@ -193,7 +193,7 @@ static void hsw_audio_codec_enable(struct drm_connector *connector,
if (intel_eld_uptodate(connector,
aud_cntrl_st2, eldv,
- aud_cntl_st, IBX_ELD_ADDRESS,
+ aud_cntl_st, IBX_ELD_ADDRESS_MASK,
hdmiw_hdmiedid))
return;
@@ -202,7 +202,7 @@ static void hsw_audio_codec_enable(struct drm_connector *connector,
I915_WRITE(aud_cntrl_st2, tmp);
tmp = I915_READ(aud_cntl_st);
- tmp &= ~IBX_ELD_ADDRESS;
+ tmp &= ~IBX_ELD_ADDRESS_MASK;
I915_WRITE(aud_cntl_st, tmp);
port = (tmp >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
DRM_DEBUG_DRIVER("port num:%d\n", port);
@@ -287,7 +287,7 @@ static void ilk_audio_codec_enable(struct drm_connector *connector,
if (intel_eld_uptodate(connector,
aud_cntrl_st2, eldv,
- aud_cntl_st, IBX_ELD_ADDRESS,
+ aud_cntl_st, IBX_ELD_ADDRESS_MASK,
hdmiw_hdmiedid))
return;
@@ -296,7 +296,7 @@ static void ilk_audio_codec_enable(struct drm_connector *connector,
I915_WRITE(aud_cntrl_st2, tmp);
tmp = I915_READ(aud_cntl_st);
- tmp &= ~IBX_ELD_ADDRESS;
+ tmp &= ~IBX_ELD_ADDRESS_MASK;
I915_WRITE(aud_cntl_st, tmp);
len = min_t(int, eld[2], 21); /* 84 bytes of hw ELD buffer */
--
1.9.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 11/18] drm/i915: rewrite hsw/bdw audio codec enable/disable sequences
2014-10-03 12:43 [PATCH 00/18] drm/i915: hdmi/dp audio rework Jani Nikula
` (9 preceding siblings ...)
2014-10-03 12:43 ` [PATCH 10/18] drm/i915: clean up and clarify audio related register defines Jani Nikula
@ 2014-10-03 12:43 ` Jani Nikula
2014-10-03 12:43 ` [PATCH 12/18] drm/i915/audio: rewrite vlv/chv and gen 5-7 audio codec enable sequence Jani Nikula
` (6 subsequent siblings)
17 siblings, 0 replies; 20+ messages in thread
From: Jani Nikula @ 2014-10-03 12:43 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, shuang.he
There's some serious confusion regarding ELD valid bit that gets set and
cleared back and forth etc. Rewrite it all based on the documented audio
codec enable/disable sequences.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/intel_audio.c | 106 +++++++++++++++----------------------
1 file changed, 44 insertions(+), 62 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_audio.c b/drivers/gpu/drm/i915/intel_audio.c
index 6e4220bdcbbf..24597e4c5cab 100644
--- a/drivers/gpu/drm/i915/intel_audio.c
+++ b/drivers/gpu/drm/i915/intel_audio.c
@@ -132,14 +132,26 @@ static void g4x_audio_codec_enable(struct drm_connector *connector,
static void hsw_audio_codec_disable(struct intel_encoder *encoder)
{
- struct drm_device *dev = encoder->base.dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
struct drm_crtc *crtc = encoder->base.crtc;
enum pipe pipe = to_intel_crtc(crtc)->pipe;
uint32_t tmp;
+ DRM_DEBUG_KMS("Disable audio codec on pipe %c\n", pipe_name(pipe));
+
+ /* Disable timestamps */
+ tmp = I915_READ(HSW_AUD_CFG(pipe));
+ tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
+ tmp |= AUD_CONFIG_N_PROG_ENABLE;
+ tmp &= ~AUD_CONFIG_UPPER_N_MASK;
+ tmp &= ~AUD_CONFIG_LOWER_N_MASK;
+ if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
+ tmp |= AUD_CONFIG_N_VALUE_INDEX;
+ I915_WRITE(HSW_AUD_CFG(pipe), tmp);
+
+ /* Invalidate ELD */
tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
- tmp &= ~((AUDIO_OUTPUT_ENABLE_A | AUDIO_ELD_VALID_A) << (pipe * 4));
+ tmp &= ~(AUDIO_ELD_VALID_A << (pipe * 4));
I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
}
@@ -149,77 +161,47 @@ static void hsw_audio_codec_enable(struct drm_connector *connector,
{
struct drm_i915_private *dev_priv = connector->dev->dev_private;
struct drm_crtc *crtc = encoder->base.crtc;
- uint8_t *eld = connector->eld;
- uint32_t eldv;
+ enum pipe pipe = to_intel_crtc(crtc)->pipe;
+ const uint8_t *eld = connector->eld;
uint32_t tmp;
int len, i;
- enum pipe pipe = to_intel_crtc(crtc)->pipe;
- enum port port;
- int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
- int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
- int aud_config = HSW_AUD_CFG(pipe);
- int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
-
- /* Audio output enable */
- DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
- tmp = I915_READ(aud_cntrl_st2);
- tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
- I915_WRITE(aud_cntrl_st2, tmp);
- POSTING_READ(aud_cntrl_st2);
-
- /* Set ELD valid state */
- tmp = I915_READ(aud_cntrl_st2);
- DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
- tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
- I915_WRITE(aud_cntrl_st2, tmp);
- tmp = I915_READ(aud_cntrl_st2);
- DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
-
- /* Enable HDMI mode */
- tmp = I915_READ(aud_config);
- DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
- /* clear N_programing_enable and N_value_index */
- tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
- I915_WRITE(aud_config, tmp);
- DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
-
- eldv = AUDIO_ELD_VALID_A << (pipe * 4);
+ DRM_DEBUG_KMS("Enable audio codec on pipe %c, %u bytes ELD\n",
+ pipe_name(pipe), eld[2]);
- if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
- I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
- else
- I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
-
- if (intel_eld_uptodate(connector,
- aud_cntrl_st2, eldv,
- aud_cntl_st, IBX_ELD_ADDRESS_MASK,
- hdmiw_hdmiedid))
- return;
+ /* Enable audio presence detect, invalidate ELD */
+ tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
+ tmp |= AUDIO_OUTPUT_ENABLE_A << (pipe * 4);
+ tmp &= ~(AUDIO_ELD_VALID_A << (pipe * 4));
+ I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
- tmp = I915_READ(aud_cntrl_st2);
- tmp &= ~eldv;
- I915_WRITE(aud_cntrl_st2, tmp);
+ intel_wait_for_vblank(dev_priv->dev, pipe);
- tmp = I915_READ(aud_cntl_st);
+ /* Reset ELD write address */
+ tmp = I915_READ(HSW_AUD_DIP_ELD_CTRL(pipe));
tmp &= ~IBX_ELD_ADDRESS_MASK;
- I915_WRITE(aud_cntl_st, tmp);
- port = (tmp >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
- DRM_DEBUG_DRIVER("port num:%d\n", port);
+ I915_WRITE(HSW_AUD_DIP_ELD_CTRL(pipe), tmp);
- len = min_t(int, eld[2], 21); /* 84 bytes of hw ELD buffer */
- DRM_DEBUG_DRIVER("ELD size %d\n", len);
+ /* Up to 84 bytes of hw ELD buffer */
+ len = min_t(int, eld[2], 21);
for (i = 0; i < len; i++)
- I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
+ I915_WRITE(HSW_AUD_EDID_DATA(pipe), *((uint32_t *)eld + i));
- tmp = I915_READ(aud_cntrl_st2);
- tmp |= eldv;
- I915_WRITE(aud_cntrl_st2, tmp);
-
- /* XXX: Transitional */
+ /* ELD valid */
tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
- tmp |= ((AUDIO_OUTPUT_ENABLE_A | AUDIO_ELD_VALID_A) << (pipe * 4));
+ tmp |= AUDIO_ELD_VALID_A << (pipe * 4);
I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
+
+ /* Enable timestamps */
+ tmp = I915_READ(HSW_AUD_CFG(pipe));
+ tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
+ tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
+ tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK;
+ if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
+ tmp |= AUD_CONFIG_N_VALUE_INDEX;
+ else
+ tmp |= audio_config_hdmi_pixel_clock(mode);
+ I915_WRITE(HSW_AUD_CFG(pipe), tmp);
}
static void ilk_audio_codec_enable(struct drm_connector *connector,
--
1.9.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 12/18] drm/i915/audio: rewrite vlv/chv and gen 5-7 audio codec enable sequence
2014-10-03 12:43 [PATCH 00/18] drm/i915: hdmi/dp audio rework Jani Nikula
` (10 preceding siblings ...)
2014-10-03 12:43 ` [PATCH 11/18] drm/i915: rewrite hsw/bdw audio codec enable/disable sequences Jani Nikula
@ 2014-10-03 12:43 ` Jani Nikula
2014-10-03 12:43 ` [PATCH 13/18] drm/i915/audio: add vlv/chv/gen5-7 audio codec disable sequence Jani Nikula
` (5 subsequent siblings)
17 siblings, 0 replies; 20+ messages in thread
From: Jani Nikula @ 2014-10-03 12:43 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, shuang.he
Similar to the hsw/bdw enable sequence rewrite.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/intel_audio.c | 58 +++++++++++++++++---------------------
1 file changed, 26 insertions(+), 32 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_audio.c b/drivers/gpu/drm/i915/intel_audio.c
index 24597e4c5cab..6a450e9333cc 100644
--- a/drivers/gpu/drm/i915/intel_audio.c
+++ b/drivers/gpu/drm/i915/intel_audio.c
@@ -210,6 +210,10 @@ static void ilk_audio_codec_enable(struct drm_connector *connector,
{
struct drm_i915_private *dev_priv = connector->dev->dev_private;
struct drm_crtc *crtc = encoder->base.crtc;
+ struct intel_digital_port *intel_dig_port =
+ enc_to_dig_port(&encoder->base);
+ enum port port = intel_dig_port->port;
+ enum pipe pipe = to_intel_crtc(crtc)->pipe;
uint8_t *eld = connector->eld;
uint32_t eldv;
uint32_t tmp;
@@ -218,8 +222,11 @@ static void ilk_audio_codec_enable(struct drm_connector *connector,
int aud_config;
int aud_cntl_st;
int aud_cntrl_st2;
- enum pipe pipe = to_intel_crtc(crtc)->pipe;
- enum port port;
+
+ DRM_DEBUG_KMS("Enable audio codec on port %c, pipe %c, %u bytes ELD\n",
+ port_name(port), pipe_name(pipe), eld[2]);
+
+ intel_wait_for_vblank(dev_priv->dev, pipe);
if (HAS_PCH_IBX(connector->dev)) {
hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
@@ -238,57 +245,44 @@ static void ilk_audio_codec_enable(struct drm_connector *connector,
aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
}
- DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
-
- if (IS_VALLEYVIEW(connector->dev)) {
- struct intel_digital_port *intel_dig_port;
-
- intel_dig_port = enc_to_dig_port(&encoder->base);
- port = intel_dig_port->port;
- } else {
- tmp = I915_READ(aud_cntl_st);
- port = (tmp >> 29) & DIP_PORT_SEL_MASK;
- /* DIP_Port_Select, 0x1 = PortB */
- }
-
- if (!port) {
- DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
- /* operate blindly on all ports */
+ if (WARN_ON(!port)) {
eldv = IBX_ELD_VALIDB;
eldv |= IBX_ELD_VALIDB << 4;
eldv |= IBX_ELD_VALIDB << 8;
} else {
- DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(port));
eldv = IBX_ELD_VALIDB << ((port - 1) * 4);
}
- if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
- I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
- else
- I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
-
- if (intel_eld_uptodate(connector,
- aud_cntrl_st2, eldv,
- aud_cntl_st, IBX_ELD_ADDRESS_MASK,
- hdmiw_hdmiedid))
- return;
-
+ /* Invalidate ELD */
tmp = I915_READ(aud_cntrl_st2);
tmp &= ~eldv;
I915_WRITE(aud_cntrl_st2, tmp);
+ /* Reset ELD write address */
tmp = I915_READ(aud_cntl_st);
tmp &= ~IBX_ELD_ADDRESS_MASK;
I915_WRITE(aud_cntl_st, tmp);
- len = min_t(int, eld[2], 21); /* 84 bytes of hw ELD buffer */
- DRM_DEBUG_DRIVER("ELD size %d\n", len);
+ /* Up to 84 bytes of hw ELD buffer */
+ len = min_t(int, eld[2], 21);
for (i = 0; i < len; i++)
I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
+ /* ELD valid */
tmp = I915_READ(aud_cntrl_st2);
tmp |= eldv;
I915_WRITE(aud_cntrl_st2, tmp);
+
+ /* Enable timestamps */
+ tmp = I915_READ(aud_config);
+ tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
+ tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
+ tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK;
+ if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
+ tmp |= AUD_CONFIG_N_VALUE_INDEX;
+ else
+ tmp |= audio_config_hdmi_pixel_clock(mode);
+ I915_WRITE(aud_config, tmp);
}
void intel_audio_codec_enable(struct intel_encoder *intel_encoder)
--
1.9.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 13/18] drm/i915/audio: add vlv/chv/gen5-7 audio codec disable sequence
2014-10-03 12:43 [PATCH 00/18] drm/i915: hdmi/dp audio rework Jani Nikula
` (11 preceding siblings ...)
2014-10-03 12:43 ` [PATCH 12/18] drm/i915/audio: rewrite vlv/chv and gen 5-7 audio codec enable sequence Jani Nikula
@ 2014-10-03 12:43 ` Jani Nikula
2014-10-03 12:43 ` [PATCH 14/18] drm/i915: enable audio codec after port Jani Nikula
` (4 subsequent siblings)
17 siblings, 0 replies; 20+ messages in thread
From: Jani Nikula @ 2014-10-03 12:43 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, shuang.he
Add support for disabling the audio codec on vlv/chv/gen5-7, similar to
hsw/bdw.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/intel_audio.c | 52 ++++++++++++++++++++++++++++++++++++++
drivers/gpu/drm/i915/intel_dp.c | 4 +++
drivers/gpu/drm/i915/intel_hdmi.c | 4 +++
3 files changed, 60 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_audio.c b/drivers/gpu/drm/i915/intel_audio.c
index 6a450e9333cc..02d993c0d743 100644
--- a/drivers/gpu/drm/i915/intel_audio.c
+++ b/drivers/gpu/drm/i915/intel_audio.c
@@ -204,6 +204,56 @@ static void hsw_audio_codec_enable(struct drm_connector *connector,
I915_WRITE(HSW_AUD_CFG(pipe), tmp);
}
+static void ilk_audio_codec_disable(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
+ struct drm_crtc *crtc = encoder->base.crtc;
+ struct intel_digital_port *intel_dig_port =
+ enc_to_dig_port(&encoder->base);
+ enum port port = intel_dig_port->port;
+ enum pipe pipe = to_intel_crtc(crtc)->pipe;
+ uint32_t tmp, eldv;
+ int aud_config;
+ int aud_cntrl_st2;
+
+ DRM_DEBUG_KMS("Disable audio codec on port %c, pipe %c\n",
+ port_name(port), pipe_name(pipe));
+
+ if (HAS_PCH_IBX(dev_priv->dev)) {
+ aud_config = IBX_AUD_CFG(pipe);
+ aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
+ } else if (IS_VALLEYVIEW(dev_priv)) {
+ aud_config = VLV_AUD_CFG(pipe);
+ aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
+ } else {
+ aud_config = CPT_AUD_CFG(pipe);
+ aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
+ }
+
+ /* Disable timestamps */
+ tmp = I915_READ(aud_config);
+ tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
+ tmp |= AUD_CONFIG_N_PROG_ENABLE;
+ tmp &= ~AUD_CONFIG_UPPER_N_MASK;
+ tmp &= ~AUD_CONFIG_LOWER_N_MASK;
+ if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
+ tmp |= AUD_CONFIG_N_VALUE_INDEX;
+ I915_WRITE(aud_config, tmp);
+
+ if (WARN_ON(!port)) {
+ eldv = IBX_ELD_VALIDB;
+ eldv |= IBX_ELD_VALIDB << 4;
+ eldv |= IBX_ELD_VALIDB << 8;
+ } else {
+ eldv = IBX_ELD_VALIDB << ((port - 1) * 4);
+ }
+
+ /* Invalidate ELD */
+ tmp = I915_READ(aud_cntrl_st2);
+ tmp &= ~eldv;
+ I915_WRITE(aud_cntrl_st2, tmp);
+}
+
static void ilk_audio_codec_enable(struct drm_connector *connector,
struct intel_encoder *encoder,
struct drm_display_mode *mode)
@@ -333,10 +383,12 @@ void intel_init_audio(struct drm_device *dev)
dev_priv->display.audio_codec_enable = g4x_audio_codec_enable;
} else if (IS_VALLEYVIEW(dev)) {
dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;
+ dev_priv->display.audio_codec_disable = ilk_audio_codec_disable;
} else if (IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8) {
dev_priv->display.audio_codec_enable = hsw_audio_codec_enable;
dev_priv->display.audio_codec_disable = hsw_audio_codec_disable;
} else if (HAS_PCH_SPLIT(dev)) {
dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;
+ dev_priv->display.audio_codec_disable = ilk_audio_codec_disable;
}
}
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 80e94def24eb..4debc13da0e6 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -2368,6 +2368,10 @@ static void intel_disable_dp(struct intel_encoder *encoder)
{
struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
struct drm_device *dev = encoder->base.dev;
+ struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
+
+ if (crtc->config.has_audio)
+ intel_audio_codec_disable(encoder);
/* Make sure the panel is off before trying to change the mode. But also
* ensure that we have vdd while we switch off the panel. */
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index f29026a1157d..f89f71e1f2ce 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -802,9 +802,13 @@ static void intel_disable_hdmi(struct intel_encoder *encoder)
struct drm_device *dev = encoder->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
+ struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
u32 temp;
u32 enable_bits = SDVO_ENABLE | SDVO_AUDIO_ENABLE;
+ if (crtc->config.has_audio)
+ intel_audio_codec_disable(encoder);
+
temp = I915_READ(intel_hdmi->hdmi_reg);
/* HW workaround for IBX, we need to move the port to transcoder A
--
1.9.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 14/18] drm/i915: enable audio codec after port
2014-10-03 12:43 [PATCH 00/18] drm/i915: hdmi/dp audio rework Jani Nikula
` (12 preceding siblings ...)
2014-10-03 12:43 ` [PATCH 13/18] drm/i915/audio: add vlv/chv/gen5-7 audio codec disable sequence Jani Nikula
@ 2014-10-03 12:43 ` Jani Nikula
2014-10-03 12:43 ` [PATCH 15/18] drm/i915/audio: add audio codec disable on g4x Jani Nikula
` (3 subsequent siblings)
17 siblings, 0 replies; 20+ messages in thread
From: Jani Nikula @ 2014-10-03 12:43 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, shuang.he
As per spec, and similar to DDI.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/intel_dp.c | 13 ++++++++-----
drivers/gpu/drm/i915/intel_hdmi.c | 15 +++++++--------
2 files changed, 15 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 4debc13da0e6..d32958fad22b 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1246,12 +1246,8 @@ static void intel_dp_prepare(struct intel_encoder *encoder)
intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
- if (crtc->config.has_audio) {
- DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
- pipe_name(crtc->pipe));
+ if (crtc->config.has_audio)
intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
- intel_audio_codec_enable(encoder);
- }
/* Split out the IBX/CPU vs CPT settings */
@@ -2541,6 +2537,7 @@ static void intel_enable_dp(struct intel_encoder *encoder)
struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
struct drm_device *dev = encoder->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
uint32_t dp_reg = I915_READ(intel_dp->output_reg);
if (WARN_ON(dp_reg & DP_PORT_EN))
@@ -2554,6 +2551,12 @@ static void intel_enable_dp(struct intel_encoder *encoder)
intel_dp_start_link_train(intel_dp);
intel_dp_complete_link_train(intel_dp);
intel_dp_stop_link_train(intel_dp);
+
+ if (crtc->config.has_audio) {
+ DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
+ pipe_name(crtc->pipe));
+ intel_audio_codec_enable(encoder);
+ }
}
static void g4x_enable_dp(struct intel_encoder *encoder)
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index f89f71e1f2ce..29baa53aef90 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -661,14 +661,6 @@ static void intel_hdmi_prepare(struct intel_encoder *encoder)
if (crtc->config.has_hdmi_sink)
hdmi_val |= HDMI_MODE_SELECT_HDMI;
- if (crtc->config.has_audio) {
- WARN_ON(!crtc->config.has_hdmi_sink);
- DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
- pipe_name(crtc->pipe));
- hdmi_val |= SDVO_AUDIO_ENABLE;
- intel_audio_codec_enable(encoder);
- }
-
if (HAS_PCH_CPT(dev))
hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe);
else if (IS_CHERRYVIEW(dev))
@@ -791,6 +783,13 @@ static void intel_enable_hdmi(struct intel_encoder *encoder)
I915_WRITE(intel_hdmi->hdmi_reg, temp);
POSTING_READ(intel_hdmi->hdmi_reg);
}
+
+ if (intel_crtc->config.has_audio) {
+ WARN_ON(!intel_crtc->config.has_hdmi_sink);
+ DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
+ pipe_name(intel_crtc->pipe));
+ intel_audio_codec_enable(encoder);
+ }
}
static void vlv_enable_hdmi(struct intel_encoder *encoder)
--
1.9.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 15/18] drm/i915/audio: add audio codec disable on g4x
2014-10-03 12:43 [PATCH 00/18] drm/i915: hdmi/dp audio rework Jani Nikula
` (13 preceding siblings ...)
2014-10-03 12:43 ` [PATCH 14/18] drm/i915: enable audio codec after port Jani Nikula
@ 2014-10-03 12:43 ` Jani Nikula
2014-10-03 12:43 ` [PATCH 16/18] drm/i915/audio: add audio codec enable debug log for g4x Jani Nikula
` (2 subsequent siblings)
17 siblings, 0 replies; 20+ messages in thread
From: Jani Nikula @ 2014-10-03 12:43 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, shuang.he
This not based on any documentation...
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/intel_audio.c | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_audio.c b/drivers/gpu/drm/i915/intel_audio.c
index 02d993c0d743..af19ecf87bb0 100644
--- a/drivers/gpu/drm/i915/intel_audio.c
+++ b/drivers/gpu/drm/i915/intel_audio.c
@@ -93,6 +93,25 @@ static bool intel_eld_uptodate(struct drm_connector *connector,
return true;
}
+static void g4x_audio_codec_disable(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
+ uint32_t eldv, tmp;
+
+ DRM_DEBUG_KMS("Disable audio codec\n");
+
+ tmp = I915_READ(G4X_AUD_VID_DID);
+ if (tmp == INTEL_AUDIO_DEVBLC || tmp == INTEL_AUDIO_DEVCL)
+ eldv = G4X_ELDV_DEVCL_DEVBLC;
+ else
+ eldv = G4X_ELDV_DEVCTG;
+
+ /* Invalidate ELD */
+ tmp = I915_READ(G4X_AUD_CNTL_ST);
+ tmp &= ~eldv;
+ I915_WRITE(G4X_AUD_CNTL_ST, tmp);
+}
+
static void g4x_audio_codec_enable(struct drm_connector *connector,
struct intel_encoder *encoder,
struct drm_display_mode *mode)
@@ -381,6 +400,7 @@ void intel_init_audio(struct drm_device *dev)
if (IS_G4X(dev)) {
dev_priv->display.audio_codec_enable = g4x_audio_codec_enable;
+ dev_priv->display.audio_codec_disable = g4x_audio_codec_disable;
} else if (IS_VALLEYVIEW(dev)) {
dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;
dev_priv->display.audio_codec_disable = ilk_audio_codec_disable;
--
1.9.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 16/18] drm/i915/audio: add audio codec enable debug log for g4x
2014-10-03 12:43 [PATCH 00/18] drm/i915: hdmi/dp audio rework Jani Nikula
` (14 preceding siblings ...)
2014-10-03 12:43 ` [PATCH 15/18] drm/i915/audio: add audio codec disable on g4x Jani Nikula
@ 2014-10-03 12:43 ` Jani Nikula
2014-10-03 12:44 ` [PATCH 17/18] drm/i915: make pipe/port based audio valid accessors easier to use Jani Nikula
2014-10-03 12:44 ` [PATCH 18/18] drm/i915/audio: add DOC comment describing HDA over HDMI/DP Jani Nikula
17 siblings, 0 replies; 20+ messages in thread
From: Jani Nikula @ 2014-10-03 12:43 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, shuang.he
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/intel_audio.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_audio.c b/drivers/gpu/drm/i915/intel_audio.c
index af19ecf87bb0..03caa8e9bf25 100644
--- a/drivers/gpu/drm/i915/intel_audio.c
+++ b/drivers/gpu/drm/i915/intel_audio.c
@@ -122,6 +122,8 @@ static void g4x_audio_codec_enable(struct drm_connector *connector,
uint32_t tmp;
int len, i;
+ DRM_DEBUG_KMS("Enable audio codec, %u bytes ELD\n", eld[2]);
+
tmp = I915_READ(G4X_AUD_VID_DID);
if (tmp == INTEL_AUDIO_DEVBLC || tmp == INTEL_AUDIO_DEVCL)
eldv = G4X_ELDV_DEVCL_DEVBLC;
--
1.9.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 17/18] drm/i915: make pipe/port based audio valid accessors easier to use
2014-10-03 12:43 [PATCH 00/18] drm/i915: hdmi/dp audio rework Jani Nikula
` (15 preceding siblings ...)
2014-10-03 12:43 ` [PATCH 16/18] drm/i915/audio: add audio codec enable debug log for g4x Jani Nikula
@ 2014-10-03 12:44 ` Jani Nikula
2014-10-03 12:44 ` [PATCH 18/18] drm/i915/audio: add DOC comment describing HDA over HDMI/DP Jani Nikula
17 siblings, 0 replies; 20+ messages in thread
From: Jani Nikula @ 2014-10-03 12:44 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, shuang.he
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 20 ++++++--------------
drivers/gpu/drm/i915/intel_audio.c | 22 ++++++++++------------
drivers/gpu/drm/i915/intel_ddi.c | 2 +-
3 files changed, 17 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b914e7932a76..04790c0f52ed 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5977,8 +5977,8 @@ enum punit_power_well {
#define IBX_ELD_ADDRESS_MASK (0x1f << 5)
#define IBX_ELD_ACK (1 << 4)
#define IBX_AUD_CNTL_ST2 0xE20C0
-#define IBX_ELD_VALIDB (1 << 0)
-#define IBX_CP_READYB (1 << 1)
+#define IBX_CP_READY(port) ((1 << 1) << (((port) - 1) * 4))
+#define IBX_ELD_VALID(port) ((1 << 0) << (((port) - 1) * 4))
#define _CPT_HDMIW_HDMIEDID_A 0xE5050
#define _CPT_HDMIW_HDMIEDID_B 0xE5150
@@ -6081,18 +6081,10 @@ enum punit_power_well {
#define HSW_AUD_PIPE_CONV_CFG 0x6507c
#define HSW_AUD_PIN_ELD_CP_VLD 0x650c0
-#define AUDIO_INACTIVE_C (1<<11)
-#define AUDIO_INACTIVE_B (1<<7)
-#define AUDIO_INACTIVE_A (1<<3)
-#define AUDIO_OUTPUT_ENABLE_A (1<<2)
-#define AUDIO_OUTPUT_ENABLE_B (1<<6)
-#define AUDIO_OUTPUT_ENABLE_C (1<<10)
-#define AUDIO_ELD_VALID_A (1<<0)
-#define AUDIO_ELD_VALID_B (1<<4)
-#define AUDIO_ELD_VALID_C (1<<8)
-#define AUDIO_CP_READY_A (1<<1)
-#define AUDIO_CP_READY_B (1<<5)
-#define AUDIO_CP_READY_C (1<<9)
+#define AUDIO_INACTIVE(trans) ((1 << 3) << ((trans) * 4))
+#define AUDIO_OUTPUT_ENABLE(trans) ((1 << 2) << ((trans) * 4))
+#define AUDIO_CP_READY(trans) ((1 << 1) << ((trans) * 4))
+#define AUDIO_ELD_VALID(trans) ((1 << 0) << ((trans) * 4))
/* HSW Power Wells */
#define HSW_PWR_WELL_BIOS 0x45400 /* CTL1 */
diff --git a/drivers/gpu/drm/i915/intel_audio.c b/drivers/gpu/drm/i915/intel_audio.c
index 03caa8e9bf25..58de48ff3585 100644
--- a/drivers/gpu/drm/i915/intel_audio.c
+++ b/drivers/gpu/drm/i915/intel_audio.c
@@ -172,7 +172,7 @@ static void hsw_audio_codec_disable(struct intel_encoder *encoder)
/* Invalidate ELD */
tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
- tmp &= ~(AUDIO_ELD_VALID_A << (pipe * 4));
+ tmp &= ~AUDIO_ELD_VALID(pipe);
I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
}
@@ -192,8 +192,8 @@ static void hsw_audio_codec_enable(struct drm_connector *connector,
/* Enable audio presence detect, invalidate ELD */
tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
- tmp |= AUDIO_OUTPUT_ENABLE_A << (pipe * 4);
- tmp &= ~(AUDIO_ELD_VALID_A << (pipe * 4));
+ tmp |= AUDIO_OUTPUT_ENABLE(pipe);
+ tmp &= ~AUDIO_ELD_VALID(pipe);
I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
intel_wait_for_vblank(dev_priv->dev, pipe);
@@ -210,7 +210,7 @@ static void hsw_audio_codec_enable(struct drm_connector *connector,
/* ELD valid */
tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
- tmp |= AUDIO_ELD_VALID_A << (pipe * 4);
+ tmp |= AUDIO_ELD_VALID(pipe);
I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
/* Enable timestamps */
@@ -262,11 +262,10 @@ static void ilk_audio_codec_disable(struct intel_encoder *encoder)
I915_WRITE(aud_config, tmp);
if (WARN_ON(!port)) {
- eldv = IBX_ELD_VALIDB;
- eldv |= IBX_ELD_VALIDB << 4;
- eldv |= IBX_ELD_VALIDB << 8;
+ eldv = IBX_ELD_VALID(PORT_B) | IBX_ELD_VALID(PORT_C) |
+ IBX_ELD_VALID(PORT_D);
} else {
- eldv = IBX_ELD_VALIDB << ((port - 1) * 4);
+ eldv = IBX_ELD_VALID(port);
}
/* Invalidate ELD */
@@ -317,11 +316,10 @@ static void ilk_audio_codec_enable(struct drm_connector *connector,
}
if (WARN_ON(!port)) {
- eldv = IBX_ELD_VALIDB;
- eldv |= IBX_ELD_VALIDB << 4;
- eldv |= IBX_ELD_VALIDB << 8;
+ eldv = IBX_ELD_VALID(PORT_B) | IBX_ELD_VALID(PORT_C) |
+ IBX_ELD_VALID(PORT_D);
} else {
- eldv = IBX_ELD_VALIDB << ((port - 1) * 4);
+ eldv = IBX_ELD_VALID(port);
}
/* Invalidate ELD */
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index ba3dccc055d4..e2a0ee3f9994 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1504,7 +1504,7 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
if (intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO)) {
temp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
- if (temp & (AUDIO_OUTPUT_ENABLE_A << (intel_crtc->pipe * 4)))
+ if (temp & AUDIO_OUTPUT_ENABLE(intel_crtc->pipe))
pipe_config->has_audio = true;
}
--
1.9.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 18/18] drm/i915/audio: add DOC comment describing HDA over HDMI/DP
2014-10-03 12:43 [PATCH 00/18] drm/i915: hdmi/dp audio rework Jani Nikula
` (16 preceding siblings ...)
2014-10-03 12:44 ` [PATCH 17/18] drm/i915: make pipe/port based audio valid accessors easier to use Jani Nikula
@ 2014-10-03 12:44 ` Jani Nikula
2014-10-03 16:22 ` Daniel Vetter
17 siblings, 1 reply; 20+ messages in thread
From: Jani Nikula @ 2014-10-03 12:44 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, shuang.he
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/intel_audio.c | 21 +++++++++++++++++++++
1 file changed, 21 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_audio.c b/drivers/gpu/drm/i915/intel_audio.c
index 58de48ff3585..6d1f8438dc4d 100644
--- a/drivers/gpu/drm/i915/intel_audio.c
+++ b/drivers/gpu/drm/i915/intel_audio.c
@@ -28,6 +28,27 @@
#include "intel_drv.h"
#include "i915_drv.h"
+/**
+ * DOC: High Definition Audio over HDMI and Display Port
+ *
+ * The graphics and audio drivers together support High Definition Audio over
+ * HDMI and Display Port. The audio programming sequences are divided into audio
+ * codec and controller enable and disable sequences. The graphics driver
+ * handles the audio codec sequences, while the audio driver handles the audio
+ * controller sequences.
+ *
+ * The disable sequences must be performed before disabling the transcoder or
+ * port. The enable sequences may only be performed after enabling the
+ * transcoder and port, and after completed link training.
+ *
+ * The codec and controller sequences could be done either parallel or serial,
+ * but generally the ELDV/PD change in the codec sequence indicates to the audio
+ * driver that the controller sequence should start. Indeed, most of the
+ * co-operation between the graphics and audio drivers is handled via audio
+ * related registers. (The notable exception is the power management, not
+ * covered here.)
+ */
+
static const struct {
int clock;
u32 config;
--
1.9.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* Re: [PATCH 18/18] drm/i915/audio: add DOC comment describing HDA over HDMI/DP
2014-10-03 12:44 ` [PATCH 18/18] drm/i915/audio: add DOC comment describing HDA over HDMI/DP Jani Nikula
@ 2014-10-03 16:22 ` Daniel Vetter
0 siblings, 0 replies; 20+ messages in thread
From: Daniel Vetter @ 2014-10-03 16:22 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx, shuang.he
On Fri, Oct 03, 2014 at 03:44:01PM +0300, Jani Nikula wrote:
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/intel_audio.c | 21 +++++++++++++++++++++
> 1 file changed, 21 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_audio.c b/drivers/gpu/drm/i915/intel_audio.c
> index 58de48ff3585..6d1f8438dc4d 100644
> --- a/drivers/gpu/drm/i915/intel_audio.c
> +++ b/drivers/gpu/drm/i915/intel_audio.c
> @@ -28,6 +28,27 @@
> #include "intel_drv.h"
> #include "i915_drv.h"
>
> +/**
> + * DOC: High Definition Audio over HDMI and Display Port
> + *
> + * The graphics and audio drivers together support High Definition Audio over
> + * HDMI and Display Port. The audio programming sequences are divided into audio
> + * codec and controller enable and disable sequences. The graphics driver
> + * handles the audio codec sequences, while the audio driver handles the audio
> + * controller sequences.
> + *
> + * The disable sequences must be performed before disabling the transcoder or
> + * port. The enable sequences may only be performed after enabling the
> + * transcoder and port, and after completed link training.
> + *
> + * The codec and controller sequences could be done either parallel or serial,
> + * but generally the ELDV/PD change in the codec sequence indicates to the audio
> + * driver that the controller sequence should start. Indeed, most of the
> + * co-operation between the graphics and audio drivers is handled via audio
> + * related registers. (The notable exception is the power management, not
> + * covered here.)
> + */
Generally when documenting a new file I also document all the non-static
functions exported to the driver. But I guess this can wait until the
functional/interface changes are merged.
Also, this should get pulled into the drm/i915 docbook in a new chapter in
the modeset section.
Otherwise I like the series, at least from a very high-level read-through.
Please sign someone up for review.
-Daniel
> +
> static const struct {
> int clock;
> u32 config;
> --
> 1.9.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 20+ messages in thread
end of thread, other threads:[~2014-10-03 16:22 UTC | newest]
Thread overview: 20+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2014-10-03 12:43 [PATCH 00/18] drm/i915: hdmi/dp audio rework Jani Nikula
2014-10-03 12:43 ` [PATCH 01/18] drm/i915: add new intel audio file to group DP/HDMI audio Jani Nikula
2014-10-03 12:43 ` [PATCH 02/18] drm/i915/audio: constify hdmi audio clock struct Jani Nikula
2014-10-03 12:43 ` [PATCH 03/18] drm/i915/audio: beat some sense into the variable types and names Jani Nikula
2014-10-03 12:43 ` [PATCH 04/18] drm/i915: pass intel_encoder to intel_write_eld Jani Nikula
2014-10-03 12:43 ` [PATCH 05/18] drm/i915/audio: pass intel_encoder on to platform specific ELD functions Jani Nikula
2014-10-03 12:43 ` [PATCH 06/18] drm/i915/audio: set ELD Conn_Type at one place Jani Nikula
2014-10-03 12:43 ` [PATCH 07/18] drm/i915/ddi: write ELD where it's supposed to be done Jani Nikula
2014-10-03 12:43 ` [PATCH 08/18] drm/i915: introduce intel_audio_codec_{enable, disable} Jani Nikula
2014-10-03 12:43 ` [PATCH 09/18] drm/i915/audio: remove misleading checks for !eld[0] Jani Nikula
2014-10-03 12:43 ` [PATCH 10/18] drm/i915: clean up and clarify audio related register defines Jani Nikula
2014-10-03 12:43 ` [PATCH 11/18] drm/i915: rewrite hsw/bdw audio codec enable/disable sequences Jani Nikula
2014-10-03 12:43 ` [PATCH 12/18] drm/i915/audio: rewrite vlv/chv and gen 5-7 audio codec enable sequence Jani Nikula
2014-10-03 12:43 ` [PATCH 13/18] drm/i915/audio: add vlv/chv/gen5-7 audio codec disable sequence Jani Nikula
2014-10-03 12:43 ` [PATCH 14/18] drm/i915: enable audio codec after port Jani Nikula
2014-10-03 12:43 ` [PATCH 15/18] drm/i915/audio: add audio codec disable on g4x Jani Nikula
2014-10-03 12:43 ` [PATCH 16/18] drm/i915/audio: add audio codec enable debug log for g4x Jani Nikula
2014-10-03 12:44 ` [PATCH 17/18] drm/i915: make pipe/port based audio valid accessors easier to use Jani Nikula
2014-10-03 12:44 ` [PATCH 18/18] drm/i915/audio: add DOC comment describing HDA over HDMI/DP Jani Nikula
2014-10-03 16:22 ` Daniel Vetter
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