From mboxrd@z Thu Jan 1 00:00:00 1970 From: Lionel Landwerlin Subject: Re: [Intel-gfx] [PATCH v7 3/3] drm/i915/icl: whitelist PS_(DEPTH|INVOCATION)_COUNT Date: Tue, 2 Jul 2019 15:32:44 +0300 Message-ID: References: <20190628120720.21682-1-lionel.g.landwerlin@intel.com> <20190628120720.21682-4-lionel.g.landwerlin@intel.com> <87woh039g5.fsf@gaia.fi.intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <87woh039g5.fsf@gaia.fi.intel.com> Content-Language: en-US Sender: stable-owner@vger.kernel.org To: Mika Kuoppala , intel-gfx@lists.freedesktop.org Cc: stable@vger.kernel.org List-Id: intel-gfx@lists.freedesktop.org On 02/07/2019 15:30, Mika Kuoppala wrote: > Lionel Landwerlin writes: > >> The same tests failing on CFL+ platforms are also failing on ICL. >> Documentation doesn't list the >> WaAllowPMDepthAndInvocationCountAccessFromUMD workaround for ICL but >> applying it fixes the same tests as CFL. > Didn't find more documentation either but I have asked > for the wa author for update. I've filed an issue on the register definition (maybe a week ago), so far no response. Hopefully you get luckier ;) -Lionel > >> v2: Use only one whitelist entry (Lionel) >> >> Signed-off-by: Lionel Landwerlin >> Tested-by: Anuj Phogat >> Cc: stable@vger.kernel.org > The register offsets are the same so we can't really do > harm with this so we go with the evidence, > > Reviewed-by: Mika Kuoppala > >> --- >> drivers/gpu/drm/i915/gt/intel_workarounds.c | 13 +++++++++++++ >> 1 file changed, 13 insertions(+) >> >> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c >> index b117583e38bb..a908d829d6bd 100644 >> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c >> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c >> @@ -1138,6 +1138,19 @@ static void icl_whitelist_build(struct intel_engine_cs *engine) >> >> /* WaEnableStateCacheRedirectToCS:icl */ >> whitelist_reg(w, GEN9_SLICE_COMMON_ECO_CHICKEN1); >> + >> + /* >> + * WaAllowPMDepthAndInvocationCountAccessFromUMD:icl >> + * >> + * This covers 4 register which are next to one another : >> + * - PS_INVOCATION_COUNT >> + * - PS_INVOCATION_COUNT_UDW >> + * - PS_DEPTH_COUNT >> + * - PS_DEPTH_COUNT_UDW >> + */ >> + whitelist_reg_ext(w, PS_INVOCATION_COUNT, >> + RING_FORCE_TO_NONPRIV_RD | >> + RING_FORCE_TO_NONPRIV_RANGE_4); >> break; >> >> case VIDEO_DECODE_CLASS: >> -- >> 2.21.0.392.gf8f6787159e >> >> _______________________________________________ >> Intel-gfx mailing list >> Intel-gfx@lists.freedesktop.org >> https://lists.freedesktop.org/mailman/listinfo/intel-gfx