From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9DADCC433FE for ; Thu, 24 Mar 2022 00:08:06 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7B43F10E456; Thu, 24 Mar 2022 00:08:05 +0000 (UTC) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id C63E710E358; Thu, 24 Mar 2022 00:08:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1648080483; x=1679616483; h=from:to:cc:subject:date:message-id:mime-version; bh=ScW1KifLvIg/rGF7pWVloW5MzZ/vex/fcHB4I2H74jk=; b=EQnt78YyV39GVUglTjrxya/tzt8fwKxKm8NCNnYLpr0HDyN1vWp0UhGM uIO8XwF6UP7X6B3wYXnNpEdQoWpQqhtHku2BH4JTl7r5gdtN6K0mOKAB7 GG/o/TUtcqxm5O5KnlsT8aVt33DYyH4/MgQSYz1Twn1xKDsznKtkf5jt7 d5ToW02CY+A0u+WFo4igCoNQt2KYn4vOTsQiydAwB77osIZ29ZXg//6R6 opfA5abGktAa6PLUr9rXLabd7KacbckxWj9WZa6+Wq+nvkjJdTGhG0W7P CI+zUZC4AbN0OX5ANRmk6L34KUGhR2c2VGQffaRxymgtPCI/iMVEOLb9f g==; X-IronPort-AV: E=McAfee;i="6200,9189,10295"; a="257965366" X-IronPort-AV: E=Sophos;i="5.90,205,1643702400"; d="scan'208,217";a="257965366" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Mar 2022 17:08:02 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.90,205,1643702400"; d="scan'208,217";a="785978024" Received: from irsmsx606.ger.corp.intel.com ([163.33.146.139]) by fmsmga006.fm.intel.com with ESMTP; 23 Mar 2022 17:08:01 -0700 Received: from fmsmsx611.amr.corp.intel.com (10.18.126.91) by IRSMSX606.ger.corp.intel.com (163.33.146.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.21; Thu, 24 Mar 2022 00:07:59 +0000 Received: from fmsmsx611.amr.corp.intel.com ([10.18.126.91]) by fmsmsx611.amr.corp.intel.com ([10.18.126.91]) with mapi id 15.01.2308.021; Wed, 23 Mar 2022 17:07:58 -0700 From: "Chery, Nanley G" To: "dri-devel@lists.freedesktop.org" , intel-gfx , "C, Ramalingam" Thread-Topic: RE: [Intel-gfx] [PATCH v5 13/19] drm/i915: Introduce new Tile 4 format Thread-Index: Adg/EpoKBUHSMXe8SgOFLlDUEvgGMw== Date: Thu, 24 Mar 2022 00:07:58 +0000 Message-ID: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-reaction: no-action dlp-version: 11.6.401.20 x-originating-ip: [10.22.254.132] Content-Type: multipart/alternative; boundary="_000_d3bcbbb51ff346219fabe4f17fba70d3intelcom_" MIME-Version: 1.0 Subject: Re: [Intel-gfx] [PATCH v5 13/19] drm/i915: Introduce new Tile 4 format X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Auld, Matthew" Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" --_000_d3bcbbb51ff346219fabe4f17fba70d3intelcom_ Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Hi all, Found an error in this description.. > From: Stanislav Lisovskiy stanislav.lisovskiy@intel.com > > This tiling layout uses 4KB tiles in a row-major layout. It has the same > shape as Tile Y at two granularities: 4KB (128B x 32) and 64B (16B x 4). = It > only differs from Tile Y at the 256B granularity in between. At this > granularity, Tile Y has a shape of 16B x 32 rows, but this tiling has a s= hape > of 64B x 8 rows. > 256B should be 512B (same feedback for the modifier description). Regards, Nanley > Reviewed-by: Imre Deak imre.deak@intel.com > Acked-by: Nanley Chery nanley.g.chery@intel.com > Signed-off-by: Stanislav Lisovskiy stanislav.lisovskiy@intel.com > --- > include/uapi/drm/drm_fourcc.h | 11 +++++++++++ > 1 file changed, 11 insertions(+) > > diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.= h > index fc0c1454d275..b73fe6797fc3 100644 > --- a/include/uapi/drm/drm_fourcc.h > +++ b/include/uapi/drm/drm_fourcc.h > @@ -572,6 +572,17 @@ extern "C" { > */ > #define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8= ) > > +/* > + * Intel Tile 4 layout > + * > + * This is a tiled layout using 4KB tiles in a row-major layout. It has = the same > + * shape as Tile Y at two granularities: 4KB (128B x 32) and 64B (16B x = 4). It > + * only differs from Tile Y at the 256B granularity in between. At this > + * granularity, Tile Y has a shape of 16B x 32 rows, but this tiling has= a shape > + * of 64B x 8 rows. > + */ > +#define I915_FORMAT_MOD_4_TILED fourcc_mod_code(INTEL, 9) > + > /* > * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks > * > --_000_d3bcbbb51ff346219fabe4f17fba70d3intelcom_ Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable

Hi all,

 

Found an error in this description..

 

> From: Stanislav Lisovskiy stanislav.lisovskiy@intel.com

>

> This tiling layout uses 4KB tiles in a row-majo= r layout. It has the same

> shape as Tile Y at two granularities: 4KB (128B= x 32) and 64B (16B x 4). It

> only differs from Tile Y at the 256B granularit= y in between. At this

> granularity, Tile Y has a shape of 16B x 32 row= s, but this tiling has a shape

> of 64B x 8 rows.

>

 

256B should be 512B (same feedback for the modifier = description).

 

Regards,

Nanley

 

> Reviewed-by: Imre Deak imre.deak@intel.com

> Acked-by: Nanley Chery nanley.g.chery@intel.com

> Signed-off-by: Stanislav Lisovskiy stanislav.lisovskiy@intel.com

> ---

>  include/uapi/drm/drm_fourcc.h | 11 +&= #43;+++++++++

>  1 file changed, 11 insertions(+)=

>

> diff --git a/include/uapi/drm/drm_fourcc.h b/in= clude/uapi/drm/drm_fourcc.h

> index fc0c1454d275..b73fe6797fc3 100644

> --- a/include/uapi/drm/drm_fourcc.h<= /p>

> +++ b/include/uapi/drm/drm_fourcc.h=

> @@ -572,6 +572,17 @@ extern "C" {=

>   */

>  #define I915_FORMAT_MOD_Y_TILED_GEN12_RC_= CCS_CC fourcc_mod_code(INTEL, 8)

> 

> +/*

> + * Intel Tile 4 layout

> + *

> + * This is a tiled layout using 4KB tiles = in a row-major layout. It has the same

> + * shape as Tile Y at two granularities: 4= KB (128B x 32) and 64B (16B x 4). It

> + * only differs from Tile Y at the 256B gr= anularity in between. At this

> + * granularity, Tile Y has a shape of 16B = x 32 rows, but this tiling has a shape

> + * of 64B x 8 rows.

> + */

> +#define I915_FORMAT_MOD_4_TILED  = ;       fourcc_mod_code(INTEL, 9)<= /p>

> +

>  /*

>   * Tiled, NV12MT, grouped in 64 (pix= els) x 32 (lines) -sized macroblocks

>   *

> 

--_000_d3bcbbb51ff346219fabe4f17fba70d3intelcom_--