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d="scan'208";a="262891365" Received: from abityuts-desk.ger.corp.intel.com (HELO localhost) ([10.245.244.254]) by orviesa008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Aug 2026 10:07:17 -0700 From: Jani Nikula To: Suraj Kandpal , intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org Cc: ankit.k.nautiyal@intel.com, Suraj Kandpal Subject: Re: [PATCH 1/3] drm/i915/ddi: add helper to compute DDI clock frequency In-Reply-To: <20260811025658.2376173-2-suraj.kandpal@intel.com> Organization: Intel Finland Oy - BIC 0357606-4 - c/o Alberga Business Park, 6 krs Bertel Jungin Aukio 5, 02600 Espoo, Finland References: <20260811025658.2376173-1-suraj.kandpal@intel.com> <20260811025658.2376173-2-suraj.kandpal@intel.com> Date: Tue, 11 Aug 2026 20:07:14 +0300 Message-ID: MIME-Version: 1.0 Content-Type: text/plain X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Tue, 11 Aug 2026, Suraj Kandpal wrote: > Add intel_ddi_link_symbol_clock() to return the DDI clock frequency for > a given port clock: > DP 8b/10b : rate / 10 rate > DP 128b/132b (UHBR) : rate / 32 (10/32) * rate > HDMI FRL : rate / 18 (10/18) * rate > HDMI TMDS : rate > > The DP case reuses intel_dp_link_symbol_clock(). > This will help in upcoming commits to decide value to be written > in DDI_CLK_VALFREQ. > > Signed-off-by: Suraj Kandpal > --- > drivers/gpu/drm/i915/display/intel_ddi.c | 11 +++++++++++ > drivers/gpu/drm/i915/display/intel_ddi.h | 1 + > 2 files changed, 12 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c > index bf5788c5bbd3..dd9064592ec9 100644 > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > @@ -1529,6 +1529,17 @@ int intel_ddi_level(struct intel_encoder *encoder, > return level; > } > > +int intel_ddi_link_symbol_clock(struct intel_encoder *encoder, int clock) > +{ > + if (intel_encoder_is_dp(encoder)) > + return intel_dp_link_symbol_clock(clock); > + > + if (intel_hdmi_is_frl(clock)) > + return DIV_ROUND_CLOSEST(clock * 10, 18); > + > + return clock; > +} > + > static void > hsw_set_signal_levels(struct intel_encoder *encoder, > const struct intel_crtc_state *crtc_state) > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.h b/drivers/gpu/drm/i915/display/intel_ddi.h > index 580ecb09b8b6..239d5a403f91 100644 > --- a/drivers/gpu/drm/i915/display/intel_ddi.h > +++ b/drivers/gpu/drm/i915/display/intel_ddi.h > @@ -81,6 +81,7 @@ void intel_ddi_sanitize_encoder_pll_mapping(struct intel_encoder *encoder); > int intel_ddi_level(struct intel_encoder *encoder, > const struct intel_crtc_state *crtc_state, > int lane); > +int intel_ddi_link_symbol_clock(struct intel_encoder *encoder, int clock); > void intel_ddi_update_active_dpll(struct intel_atomic_state *state, > struct intel_encoder *encoder, > struct intel_crtc *crtc); -- Jani Nikula, Intel