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From: "Teres Alexis, Alan Previn" <alan.previn.teres.alexis@intel.com>
To: "Brost, Matthew" <matthew.brost@intel.com>,
	"Harrison, John C" <john.c.harrison@intel.com>,
	"De Marchi, Lucas" <lucas.demarchi@intel.com>
Cc: "intel-gfx@lists.freedesktop.org" <intel-gfx@lists.freedesktop.org>
Subject: Re: [Intel-gfx] [PATCH v5 01/10] drm/i915/guc: Update GuC ADS size for error capture lists
Date: Thu, 3 Feb 2022 20:37:03 +0000	[thread overview]
Message-ID: <d96b56cd199796f429263ebb5335d97dfd2d9e3d.camel@intel.com> (raw)
In-Reply-To: <20220203200453.jrxhact4bcmwfpw7@ldmartin-desk2>

I can refactor my code to enforce an owner module to only return the size and an interim
buffer pointer (kzalloc, not io mem) and have ADS memcpy from that pointer into the ADS
substructure pointer.. 

But I hope we can make it a rule that its okay for an external owner-module to 
know and define the layout of the 2nd level substructure layout. This would allow
future new ADS substructure to have separate owner-modules handle the definition
of the substructure layout

something like this:

guc_ads_top_fwif.h

ADS owns top level ADS
{
    u32 ptr1;// substruct_foo1
    u32 ptr2;// substruct_foo2
    u32 ptr3;// substruct_foo3
	...
}

guc_capture_private.h

substruct_foo



So putting aside the fact that already have ADS containing the knowledge for
golden context,  register-save-restore, and others, but moving forward i am hoping
we can avoid piling on more and more unrelated low level knowledge inside of ADS.

The the error capture substructure layout has awareness of per PF-vs-VF, global vs
engine-class vs engine-instance and other fuse-specific awareness. So i am hoping
we can allow other moules to own the definition and parsing of the substructure
layout.

...alan


On Thu, 2022-02-03 at 12:04 -0800, Lucas De Marchi wrote:
> On Thu, Feb 03, 2022 at 11:03:24AM -0800, Matthew Brost wrote:
> > On Wed, Jan 26, 2022 at 02:46:19PM -0800, Lucas De Marchi wrote:
> > > On Wed, Jan 26, 2022 at 02:48:13AM -0800, Alan Previn wrote:
> > > > Update GuC ADS size allocation to include space for
> > > > the lists of error state capture register descriptors.
> > > > 
> > > > Also, populate the lists of registers we want GuC to report back to
> > > > Host on engine reset events. This list should include global,
> > > > engine-class and engine-instance registers for every engine-class
> > > > type on the current hardware.
> > > > 
> > > > NOTE: Start with a sample table of register lists to layout the
> > > > framework before adding real registers in subsequent patch.
> > > > 
> > > > Signed-off-by: Alan Previn <alan.previn.teres.alexis@intel.com>
> > > > ---
> > > 
> > > ...
> > > 
> > > > static void __guc_ads_init(struct intel_guc *guc)
> > > > {
> > > > 	struct intel_gt *gt = guc_to_gt(guc);
> > > > @@ -573,9 +553,9 @@ static void __guc_ads_init(struct intel_guc *guc)
> > > > 
> > > > 	base = intel_guc_ggtt_offset(guc, guc->ads_vma);
> > > > 
> > > > -	/* Capture list for hang debug */
> > > > -	guc_capture_list_init(guc, blob);
> > > > -
> > > > +	/* Lists for error capture debug */
> > > > +	intel_guc_capture_prep_lists(guc, (struct guc_ads *)blob, base,
> > > 
> > > no, please don't cast/export struct guc_ads like this. We can't really
> > > dereference it since it may be in IO memory.
> > > 
> > > See https://patchwork.freedesktop.org/series/99378/ with the huge
> > > refactor in this file to make it conform to the rules of accessing IO
> > > memory.
> > > 
> > > Maybe this list could be appended in the same reglist buffer and we just
> > > copy it once to its final location, like we are doing with the reglist?
> > > 
> > 
> > Agree with Lucas here, let's create the capture list on probe and store
> > it somewhere in the device data. On ADS population this more or less
> > turns into a memcpy (or after Lucas's series a dma-buf-map call). And on
> > fini, just free to stored data. The create capture list IMO is fine to
> > be done in an external file and return the data to the ADS code but
> > let's make sure everyone is on board with that. Maybe ping Lucas
> > directly about this?
> 
> yeah, sounds good to me. My worry is exporting ADS struct layout to
> other compilation units. Asking for the entire ads blob
> (or what would be dma_buf_map in my patches, or iosys_map in the new
> version I will send soon) could quickly spread too much knowledge about it to
> the rest of the driver.
> 
I'm in partial disagreement with above. Based on above statement, are we enforcing
that we must always continue to only have ADS know the 2nd level blobl structure layout?
Doesn't that also force that intelligence of knowing its substructure contents to
always be in ADS only? So ADS C file continues to grow larger and larger with completely
orthogonal domain specific knowledge? (golden context: engine info,
error-capture: debug registers, etc..).
I believe ADS should really let the substructure headers be accessible to external
modules to deal with the parsing, size determination and preparing its contents.

NOTE: see my next comment specifically regarding the pointer access.

> I think we should at most export the speficic offset inside the buffer
> another compilation unit can fill out. In that case with the
> iosys_buf API we would return a shallow copy of our guc->ads_map +
> offset.
> 
> And the other alternative would be as you suggested: save the list in a
> temporary buffer and when needed call intel_guc_ads() to populate that
> into ads in the right place.
> 

Alan: The first part of above is already what is happening in my series today,
we have a seperate register list  in the intel_guc_capture module
that also determines (based on device and fusing) which registers
to include or exclude. There is are static global lists and
per-gt-allocated lists (based on fuse masks). The latter
is not in current rev but already commented as planned change.

So in response to the original review comment, I can change this
patch so that the ADS gets a regular heap-kzalloc-allocated pointer and
size from the error-capture module and ADS do the copying into the
io-mem ptr but i want to ensure the layout of the error-capture 
lists are not private to ADS only.

Are we okay with that?

> The integration with iosys-map I can figure out if my patch series lands
> after this one, or I can help rebasing this otherwise. But IMO we
> should not pass the plain blob pointer around regardless of iosys-map.
> 
> 
> thanks
> Lucas De Marchi
> 
> > Specific patch Lucas's is referencing:
> > https://patchwork.freedesktop.org/patch/471051/?series=99378&rev=1
> > 
> > Matt
> > 
> > > Lucas De Marchi


  reply	other threads:[~2022-02-03 20:37 UTC|newest]

Thread overview: 51+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-01-26 10:48 [Intel-gfx] [PATCH v5 00/10] Add GuC Error Capture Support Alan Previn
2022-01-26 10:48 ` [Intel-gfx] [PATCH v5 01/10] drm/i915/guc: Update GuC ADS size for error capture lists Alan Previn
2022-01-26 18:09   ` Jani Nikula
2022-01-26 18:15   ` Jani Nikula
2022-01-26 22:46   ` Lucas De Marchi
2022-02-03 19:03     ` Matthew Brost
2022-02-03 20:04       ` Lucas De Marchi
2022-02-03 20:37         ` Teres Alexis, Alan Previn [this message]
2022-02-03 20:40           ` Teres Alexis, Alan Previn
2022-02-03 21:40             ` Lucas De Marchi
2022-02-03 21:58               ` Teres Alexis, Alan Previn
2022-01-26 10:48 ` [Intel-gfx] [PATCH v5 02/10] drm/i915/guc: Add XE_LP registers for GuC error state capture Alan Previn
2022-01-26 18:13   ` Jani Nikula
2022-01-26 21:46     ` Teres Alexis, Alan Previn
2022-01-27  9:30       ` Jani Nikula
2022-01-28 16:54         ` Teres Alexis, Alan Previn
2022-01-26 10:48 ` [Intel-gfx] [PATCH v5 03/10] drm/i915/guc: Add DG2 " Alan Previn
2022-02-05  1:28   ` Umesh Nerlige Ramappa
2022-02-10  5:17     ` Teres Alexis, Alan Previn
2022-02-11 19:24     ` Teres Alexis, Alan Previn
2022-01-26 10:48 ` [Intel-gfx] [PATCH v5 04/10] drm/i915/guc: Add Gen9 " Alan Previn
2022-02-07 19:14   ` Umesh Nerlige Ramappa
2022-01-26 10:48 ` [Intel-gfx] [PATCH v5 05/10] drm/i915/guc: Add GuC's error state capture output structures Alan Previn
2022-01-26 10:48 ` [Intel-gfx] [PATCH v5 06/10] drm/i915/guc: Update GuC's log-buffer-state access for error capture Alan Previn
2022-01-27  4:26   ` Teres Alexis, Alan Previn
2022-02-04 18:19   ` Matthew Brost
2022-02-08 19:38     ` Teres Alexis, Alan Previn
2022-02-08 22:18       ` Matthew Brost
2022-02-08 22:55         ` Teres Alexis, Alan Previn
2022-02-09  3:34           ` Matthew Brost
2022-02-09  3:41             ` Matthew Brost
2022-02-09  3:51             ` Teres Alexis, Alan Previn
2022-02-14 19:20               ` Teres Alexis, Alan Previn
2022-02-15  1:22                 ` Teres Alexis, Alan Previn
2022-01-26 10:48 ` [Intel-gfx] [PATCH v5 07/10] drm/i915/guc: Extract GuC error capture lists on G2H notification Alan Previn
2022-02-11  1:36   ` Umesh Nerlige Ramappa
2022-02-13 19:47     ` Teres Alexis, Alan Previn
2022-02-17 19:21       ` Umesh Nerlige Ramappa
2022-02-25  7:21         ` Teres Alexis, Alan Previn
2022-01-26 10:48 ` [Intel-gfx] [PATCH v5 08/10] drm/i915/guc: Plumb GuC-capture into gpu_coredump Alan Previn
2022-02-11  2:11   ` Umesh Nerlige Ramappa
2022-02-12  0:31     ` Teres Alexis, Alan Previn
2022-02-12  0:38     ` Teres Alexis, Alan Previn
2022-01-26 10:48 ` [Intel-gfx] [PATCH v5 09/10] drm/i915/guc: Follow legacy register names Alan Previn
2022-02-03 19:09   ` Matthew Brost
2022-02-04 18:53     ` Teres Alexis, Alan Previn
2022-01-26 10:48 ` [Intel-gfx] [PATCH v5 10/10] drm/i915/guc: Print the GuC error capture output register list Alan Previn
2022-02-07 21:43   ` Umesh Nerlige Ramappa
2022-01-26 18:51 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add GuC Error Capture Support (rev5) Patchwork
2022-01-26 18:52 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-01-26 19:25 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork

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