[PATCH 0/8] drm-intel-collector - update

[PATCH 0/8] drm-intel-collector - update

[Rodrigo Vivi]

This is another drm-intel-collector updated notice:
http://cgit.freedesktop.org/~vivijim/drm-intel/log/?h=drm-intel-collector

Here goes the update list in order for better reviewers assignment:

Patch     drm/i915: Make the physical object coherent with GTT - Reviewed-by: Ville
Patch     drm/i915: Specify bsd rings through exec flag - Reviewer: Rodrigo
Patch     drm/i915: add I915_PARAM_HAS_BSD2 to i915_getparam - Reviewer: Rodrigo
Patch     drm/i915: Move the ban period onto the context - Reviewer: Mika
Patch     drm/i915: Add ioctl to set per-context parameters - Reviewer: Rodrigo
Patch     drm/i915: Put logical pipe_control emission into a helper. - Reviewer: Mika
Patch     drm/i915: Add WaCsStallBeforeStateCacheInvalidate:bdw, chv to logical ring - Reviewer: Mika
Patch     drm/i915: Wait thread status on gen8+ fw sequence - Reviewer: Ville

Hi all,

First of all thanks for Nacks and coments on previous round. 

I still need to investigate why so big difference on PRTS when puting testing x collector.
But meanwhile let me do another round. This time I just collected one more and removed the Nacks.

This round coverred the gap on drm-intel-testing updates from Oct 03 to Oct 24.

I volunteered myself, Ville and Mika to some Reviews here. Please let me know if this list is ok or other
people should be reviewing them.

Thanks in advance,
Rodrigo.


Chris Wilson (3):
  drm/i915: Make the physical object coherent with GTT
  drm/i915: Move the ban period onto the context
  drm/i915: Add ioctl to set per-context parameters

Mika Kuoppala (1):
  drm/i915: Wait thread status on gen8+ fw sequence

Rodrigo Vivi (2):
  drm/i915: Put logical pipe_control emission into a helper.
  drm/i915: Add WaCsStallBeforeStateCacheInvalidate:bdw, chv to logical
    ring

Zhipeng Gong (2):
  drm/i915: Specify bsd rings through exec flag
  drm/i915: add I915_PARAM_HAS_BSD2 to i915_getparam

 drivers/gpu/drm/i915/i915_dma.c            |   8 ++
 drivers/gpu/drm/i915/i915_drv.h            |  15 ++-
 drivers/gpu/drm/i915/i915_gem.c            | 210 ++++++++++++++++++++---------
 drivers/gpu/drm/i915/i915_gem_context.c    |  71 ++++++++++
 drivers/gpu/drm/i915/i915_gem_execbuffer.c |  19 ++-
 drivers/gpu/drm/i915/intel_dp.c            |   3 +
 drivers/gpu/drm/i915/intel_lrc.c           |  41 ++++--
 drivers/gpu/drm/i915/intel_uncore.c        |   3 +-
 include/uapi/drm/i915_drm.h                |  22 ++-
 9 files changed, 307 insertions(+), 85 deletions(-)

-- 
1.9.3

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[PATCH 1/8] drm/i915: Make the physical object coherent with GTT

[Rodrigo Vivi]

From: Chris Wilson <chris@chris-wilson.co.uk>

Currently objects for which the hardware needs a contiguous physical
address are allocated a shadow backing storage to satisfy the contraint.
This shadow buffer is not wired into the normal obj->pages and so the
physical object is incoherent with accesses via the GPU, GTT and CPU. By
setting up the appropriate scatter-gather table, we can allow userspace
to access the physical object via either a GTT mmaping of or by rendering
into the GEM bo. However, keeping the CPU mmap of the shmemfs backing
storage coherent with the contiguous shadow is not yet possible.
Fortuituously, CPU mmaps of objects requiring physical addresses are not
expected to be coherent anyway.

This allows the physical constraint of the GEM object to be transparent
to userspace and allow it to efficiently render into or update them via
the GTT and GPU.

v2: Fix leak of pci handle spotted by Ville
v3: Remove the now duplicate call to detach_phys_object during free.
v4: Wait for rendering before pwrite. As this patch makes it possible to
render into the phys object, we should make it correct as well!

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/i915_dma.c |   3 +
 drivers/gpu/drm/i915/i915_drv.h |   6 +-
 drivers/gpu/drm/i915/i915_gem.c | 207 +++++++++++++++++++++++++++-------------
 include/uapi/drm/i915_drm.h     |   1 +
 4 files changed, 150 insertions(+), 67 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 9a73533..5dc37f0 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -1027,6 +1027,9 @@ static int i915_getparam(struct drm_device *dev, void *data,
 	case I915_PARAM_CMD_PARSER_VERSION:
 		value = i915_cmd_parser_get_version();
 		break;
+	case I915_PARAM_HAS_COHERENT_PHYS_GTT:
+		value = 1;
+		break;
 	default:
 		DRM_DEBUG("Unknown parameter %d\n", param->param);
 		return -EINVAL;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 8fb8eba..1219282 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1957,10 +1957,10 @@ struct drm_i915_gem_object {
 	unsigned long user_pin_count;
 	struct drm_file *pin_filp;
 
-	/** for phy allocated objects */
-	struct drm_dma_handle *phys_handle;
-
 	union {
+		/** for phy allocated objects */
+		struct drm_dma_handle *phys_handle;
+
 		struct i915_gem_userptr {
 			uintptr_t ptr;
 			unsigned read_only :1;
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 3e0cabe..86cf428 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -208,40 +208,137 @@ i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
 	return 0;
 }
 
-static void i915_gem_object_detach_phys(struct drm_i915_gem_object *obj)
+static int
+i915_gem_object_get_pages_phys(struct drm_i915_gem_object *obj)
 {
-	drm_dma_handle_t *phys = obj->phys_handle;
+	struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
+	char *vaddr = obj->phys_handle->vaddr;
+	struct sg_table *st;
+	struct scatterlist *sg;
+	int i;
 
-	if (!phys)
-		return;
+	if (WARN_ON(i915_gem_object_needs_bit17_swizzle(obj)))
+		return -EINVAL;
+
+	for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
+		struct page *page;
+		char *src;
+
+		page = shmem_read_mapping_page(mapping, i);
+		if (IS_ERR(page))
+			return PTR_ERR(page);
+
+		src = kmap_atomic(page);
+		memcpy(vaddr, src, PAGE_SIZE);
+		drm_clflush_virt_range(vaddr, PAGE_SIZE);
+		kunmap_atomic(src);
+
+		page_cache_release(page);
+		vaddr += PAGE_SIZE;
+	}
+
+	i915_gem_chipset_flush(obj->base.dev);
+
+	st = kmalloc(sizeof(*st), GFP_KERNEL);
+	if (st == NULL)
+		return -ENOMEM;
+
+	if (sg_alloc_table(st, 1, GFP_KERNEL)) {
+		kfree(st);
+		return -ENOMEM;
+	}
+
+	sg = st->sgl;
+	sg->offset = 0;
+	sg->length = obj->base.size;
 
-	if (obj->madv == I915_MADV_WILLNEED) {
+	sg_dma_address(sg) = obj->phys_handle->busaddr;
+	sg_dma_len(sg) = obj->base.size;
+
+	obj->pages = st;
+	obj->has_dma_mapping = true;
+	return 0;
+}
+
+static void
+i915_gem_object_put_pages_phys(struct drm_i915_gem_object *obj)
+{
+	int ret;
+
+	BUG_ON(obj->madv == __I915_MADV_PURGED);
+
+	ret = i915_gem_object_set_to_cpu_domain(obj, true);
+	if (ret) {
+		/* In the event of a disaster, abandon all caches and
+		 * hope for the best.
+		 */
+		WARN_ON(ret != -EIO);
+		obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
+	}
+
+	if (obj->madv == I915_MADV_DONTNEED)
+		obj->dirty = 0;
+
+	if (obj->dirty) {
 		struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
-		char *vaddr = phys->vaddr;
+		char *vaddr = obj->phys_handle->vaddr;
 		int i;
 
 		for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
-			struct page *page = shmem_read_mapping_page(mapping, i);
-			if (!IS_ERR(page)) {
-				char *dst = kmap_atomic(page);
-				memcpy(dst, vaddr, PAGE_SIZE);
-				drm_clflush_virt_range(dst, PAGE_SIZE);
-				kunmap_atomic(dst);
-
-				set_page_dirty(page);
+			struct page *page;
+			char *dst;
+
+			page = shmem_read_mapping_page(mapping, i);
+			if (IS_ERR(page))
+				continue;
+
+			dst = kmap_atomic(page);
+			drm_clflush_virt_range(vaddr, PAGE_SIZE);
+			memcpy(dst, vaddr, PAGE_SIZE);
+			kunmap_atomic(dst);
+
+			set_page_dirty(page);
+			if (obj->madv == I915_MADV_WILLNEED)
 				mark_page_accessed(page);
-				page_cache_release(page);
-			}
+			page_cache_release(page);
 			vaddr += PAGE_SIZE;
 		}
-		i915_gem_chipset_flush(obj->base.dev);
+		obj->dirty = 0;
 	}
 
-#ifdef CONFIG_X86
-	set_memory_wb((unsigned long)phys->vaddr, phys->size / PAGE_SIZE);
-#endif
-	drm_pci_free(obj->base.dev, phys);
-	obj->phys_handle = NULL;
+	sg_free_table(obj->pages);
+	kfree(obj->pages);
+
+	obj->has_dma_mapping = false;
+}
+
+static void
+i915_gem_object_release_phys(struct drm_i915_gem_object *obj)
+{
+	drm_pci_free(obj->base.dev, obj->phys_handle);
+}
+
+static const struct drm_i915_gem_object_ops i915_gem_phys_ops = {
+	.get_pages = i915_gem_object_get_pages_phys,
+	.put_pages = i915_gem_object_put_pages_phys,
+	.release = i915_gem_object_release_phys,
+};
+
+static int
+drop_pages(struct drm_i915_gem_object *obj)
+{
+	struct i915_vma *vma, *next;
+	int ret;
+
+	drm_gem_object_reference(&obj->base);
+	list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link)
+		if (i915_vma_unbind(vma))
+			break;
+
+	ret = i915_gem_object_put_pages(obj);
+	drm_gem_object_unreference(&obj->base);
+
+	return ret;
 }
 
 int
@@ -249,9 +346,7 @@ i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
 			    int align)
 {
 	drm_dma_handle_t *phys;
-	struct address_space *mapping;
-	char *vaddr;
-	int i;
+	int ret;
 
 	if (obj->phys_handle) {
 		if ((unsigned long)obj->phys_handle->vaddr & (align -1))
@@ -266,41 +361,19 @@ i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
 	if (obj->base.filp == NULL)
 		return -EINVAL;
 
+	ret = drop_pages(obj);
+	if (ret)
+		return ret;
+
 	/* create a new object */
 	phys = drm_pci_alloc(obj->base.dev, obj->base.size, align);
 	if (!phys)
 		return -ENOMEM;
 
-	vaddr = phys->vaddr;
-#ifdef CONFIG_X86
-	set_memory_wc((unsigned long)vaddr, phys->size / PAGE_SIZE);
-#endif
-	mapping = file_inode(obj->base.filp)->i_mapping;
-	for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
-		struct page *page;
-		char *src;
-
-		page = shmem_read_mapping_page(mapping, i);
-		if (IS_ERR(page)) {
-#ifdef CONFIG_X86
-			set_memory_wb((unsigned long)phys->vaddr, phys->size / PAGE_SIZE);
-#endif
-			drm_pci_free(obj->base.dev, phys);
-			return PTR_ERR(page);
-		}
-
-		src = kmap_atomic(page);
-		memcpy(vaddr, src, PAGE_SIZE);
-		kunmap_atomic(src);
-
-		mark_page_accessed(page);
-		page_cache_release(page);
-
-		vaddr += PAGE_SIZE;
-	}
-
 	obj->phys_handle = phys;
-	return 0;
+	obj->ops = &i915_gem_phys_ops;
+
+	return i915_gem_object_get_pages(obj);
 }
 
 static int
@@ -311,6 +384,14 @@ i915_gem_phys_pwrite(struct drm_i915_gem_object *obj,
 	struct drm_device *dev = obj->base.dev;
 	void *vaddr = obj->phys_handle->vaddr + args->offset;
 	char __user *user_data = to_user_ptr(args->data_ptr);
+	int ret;
+
+	/* We manually control the domain here and pretend that it
+	 * remains coherent i.e. in the GTT domain, like shmem_pwrite.
+	 */
+	ret = i915_gem_object_wait_rendering(obj, false);
+	if (ret)
+		return ret;
 
 	if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) {
 		unsigned long unwritten;
@@ -326,6 +407,7 @@ i915_gem_phys_pwrite(struct drm_i915_gem_object *obj,
 			return -EFAULT;
 	}
 
+	drm_clflush_virt_range(vaddr, args->size);
 	i915_gem_chipset_flush(dev);
 	return 0;
 }
@@ -1046,11 +1128,6 @@ i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
 	 * pread/pwrite currently are reading and writing from the CPU
 	 * perspective, requiring manual detiling by the client.
 	 */
-	if (obj->phys_handle) {
-		ret = i915_gem_phys_pwrite(obj, args, file);
-		goto out;
-	}
-
 	if (obj->tiling_mode == I915_TILING_NONE &&
 	    obj->base.write_domain != I915_GEM_DOMAIN_CPU &&
 	    cpu_write_needs_clflush(obj)) {
@@ -1060,8 +1137,12 @@ i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
 		 * textures). Fallback to the shmem path in that case. */
 	}
 
-	if (ret == -EFAULT || ret == -ENOSPC)
-		ret = i915_gem_shmem_pwrite(dev, obj, args, file);
+	if (ret == -EFAULT || ret == -ENOSPC) {
+		if (obj->phys_handle)
+			ret = i915_gem_phys_pwrite(obj, args, file);
+		else
+			ret = i915_gem_shmem_pwrite(dev, obj, args, file);
+	}
 
 out:
 	drm_gem_object_unreference(&obj->base);
@@ -3509,7 +3590,7 @@ i915_gem_clflush_object(struct drm_i915_gem_object *obj,
 	 * Stolen memory is always coherent with the GPU as it is explicitly
 	 * marked as wc by the system, or the system is cache-coherent.
 	 */
-	if (obj->stolen)
+	if (obj->stolen || obj->phys_handle)
 		return false;
 
 	/* If the GPU is snooping the contents of the CPU cache,
@@ -4471,8 +4552,6 @@ void i915_gem_free_object(struct drm_gem_object *gem_obj)
 		}
 	}
 
-	i915_gem_object_detach_phys(obj);
-
 	/* Stolen objects don't hold a ref, but do hold pin count. Fix that up
 	 * before progressing. */
 	if (obj->stolen)
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 2ec0efc..2502622 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -340,6 +340,7 @@ typedef struct drm_i915_irq_wait {
 #define I915_PARAM_HAS_EXEC_HANDLE_LUT   26
 #define I915_PARAM_HAS_WT     	 	 27
 #define I915_PARAM_CMD_PARSER_VERSION	 28
+#define I915_PARAM_HAS_COHERENT_PHYS_GTT 29
 
 typedef struct drm_i915_getparam {
 	int param;
-- 
1.9.3

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[PATCH 2/8] drm/i915: Specify bsd rings through exec flag

[Rodrigo Vivi]

From: Zhipeng Gong <zhipeng.gong@intel.com>

On Broadwell GT3 we have 2 Video Command Streamers (VCS), but userspace
has no control when using VCS1 or VCS2. This patch introduces a mechanism
to avoid the default ping-pong mode and use one specific ring through
execution flag.

v2: fix whitespace (Rodrigo)

Signed-off-by: Zhipeng Gong <zhipeng.gong@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/i915_gem_execbuffer.c | 19 +++++++++++++++++--
 drivers/gpu/drm/i915/intel_dp.c            |  3 +++
 include/uapi/drm/i915_drm.h                |  8 +++++++-
 3 files changed, 27 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index e1ed85a..d9081ec 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -1273,8 +1273,23 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
 	else if ((args->flags & I915_EXEC_RING_MASK) == I915_EXEC_BSD) {
 		if (HAS_BSD2(dev)) {
 			int ring_id;
-			ring_id = gen8_dispatch_bsd_ring(dev, file);
-			ring = &dev_priv->ring[ring_id];
+
+			switch (args->flags & I915_EXEC_BSD_MASK) {
+			case I915_EXEC_BSD_DEFAULT:
+				ring_id = gen8_dispatch_bsd_ring(dev, file);
+				ring = &dev_priv->ring[ring_id];
+				break;
+			case I915_EXEC_BSD_RING1:
+				ring = &dev_priv->ring[VCS];
+				break;
+			case I915_EXEC_BSD_RING2:
+				ring = &dev_priv->ring[VCS2];
+				break;
+			default:
+				DRM_DEBUG("execbuf with unknown bsd ring: %d\n",
+					  (int)(args->flags & I915_EXEC_BSD_MASK));
+				return -EINVAL;
+			}
 		} else
 			ring = &dev_priv->ring[VCS];
 	} else
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index ceb528f..a8c9e47 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -4802,6 +4802,9 @@ intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
 		if (HAS_PCH_SPLIT(dev)) {
 			if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
 				goto mst_fail;
+		if (!intel_dp->output_reg)
+			goto mst_fail;
+
 		} else {
 			if (g4x_digital_port_connected(dev, intel_dig_port) != 1)
 				goto mst_fail;
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 2502622..fcb16bf 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -737,7 +737,13 @@ struct drm_i915_gem_execbuffer2 {
  */
 #define I915_EXEC_HANDLE_LUT		(1<<12)
 
-#define __I915_EXEC_UNKNOWN_FLAGS -(I915_EXEC_HANDLE_LUT<<1)
+/** Used for switching BSD rings on the platforms with two BSD rings */
+#define I915_EXEC_BSD_MASK		(3<<13)
+#define I915_EXEC_BSD_DEFAULT		(0<<13) /* default ping-pong mode */
+#define I915_EXEC_BSD_RING1		(1<<13)
+#define I915_EXEC_BSD_RING2		(2<<13)
+
+#define __I915_EXEC_UNKNOWN_FLAGS -(1<<15)
 
 #define I915_EXEC_CONTEXT_ID_MASK	(0xffffffff)
 #define i915_execbuffer2_set_context_id(eb2, context) \
-- 
1.9.3

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Re: [PATCH 2/8] drm/i915: Specify bsd rings through exec flag

[Rodrigo Vivi]

On Mon, Nov 10, 2014 at 4:52 AM, Rodrigo Vivi <rodrigo.vivi@intel.com> wrote:
> From: Zhipeng Gong <zhipeng.gong@intel.com>
>
> On Broadwell GT3 we have 2 Video Command Streamers (VCS), but userspace
> has no control when using VCS1 or VCS2. This patch introduces a mechanism
> to avoid the default ping-pong mode and use one specific ring through
> execution flag.
>
> v2: fix whitespace (Rodrigo)
>
> Signed-off-by: Zhipeng Gong <zhipeng.gong@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_gem_execbuffer.c | 19 +++++++++++++++++--
>  drivers/gpu/drm/i915/intel_dp.c            |  3 +++
>  include/uapi/drm/i915_drm.h                |  8 +++++++-
>  3 files changed, 27 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> index e1ed85a..d9081ec 100644
> --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> @@ -1273,8 +1273,23 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
>         else if ((args->flags & I915_EXEC_RING_MASK) == I915_EXEC_BSD) {
>                 if (HAS_BSD2(dev)) {
>                         int ring_id;
> -                       ring_id = gen8_dispatch_bsd_ring(dev, file);
> -                       ring = &dev_priv->ring[ring_id];
> +
> +                       switch (args->flags & I915_EXEC_BSD_MASK) {
> +                       case I915_EXEC_BSD_DEFAULT:
> +                               ring_id = gen8_dispatch_bsd_ring(dev, file);
> +                               ring = &dev_priv->ring[ring_id];
> +                               break;
> +                       case I915_EXEC_BSD_RING1:
> +                               ring = &dev_priv->ring[VCS];
> +                               break;
> +                       case I915_EXEC_BSD_RING2:
> +                               ring = &dev_priv->ring[VCS2];
> +                               break;
> +                       default:
> +                               DRM_DEBUG("execbuf with unknown bsd ring: %d\n",
> +                                         (int)(args->flags & I915_EXEC_BSD_MASK));
> +                               return -EINVAL;
> +                       }
>                 } else
>                         ring = &dev_priv->ring[VCS];
>         } else
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index ceb528f..a8c9e47 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -4802,6 +4802,9 @@ intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
>                 if (HAS_PCH_SPLIT(dev)) {
>                         if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
>                                 goto mst_fail;
> +               if (!intel_dp->output_reg)
> +                       goto mst_fail;
> +

I think this shouldn't be here

>                 } else {
>                         if (g4x_digital_port_connected(dev, intel_dig_port) != 1)
>                                 goto mst_fail;
> diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> index 2502622..fcb16bf 100644
> --- a/include/uapi/drm/i915_drm.h
> +++ b/include/uapi/drm/i915_drm.h
> @@ -737,7 +737,13 @@ struct drm_i915_gem_execbuffer2 {
>   */
>  #define I915_EXEC_HANDLE_LUT           (1<<12)
>
> -#define __I915_EXEC_UNKNOWN_FLAGS -(I915_EXEC_HANDLE_LUT<<1)
> +/** Used for switching BSD rings on the platforms with two BSD rings */
> +#define I915_EXEC_BSD_MASK             (3<<13)
> +#define I915_EXEC_BSD_DEFAULT          (0<<13) /* default ping-pong mode */
> +#define I915_EXEC_BSD_RING1            (1<<13)
> +#define I915_EXEC_BSD_RING2            (2<<13)
> +
> +#define __I915_EXEC_UNKNOWN_FLAGS -(1<<15)

This is inverted and using one bit more than needed.
Should be -(14<<1) right?!

>
>  #define I915_EXEC_CONTEXT_ID_MASK      (0xffffffff)
>  #define i915_execbuffer2_set_context_id(eb2, context) \
> --
> 1.9.3
>
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
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Blog: http://blog.vivi.eng.br
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[PATCH 3/8] drm/i915: add I915_PARAM_HAS_BSD2 to i915_getparam

[Rodrigo Vivi]

From: Zhipeng Gong <zhipeng.gong@intel.com>

This will let userland only try to use the new ring
when the appropriate kernel is present

Signed-off-by: Zhipeng Gong <zhipeng.gong@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/i915_dma.c | 3 +++
 include/uapi/drm/i915_drm.h     | 1 +
 2 files changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 5dc37f0..1c145ed 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -979,6 +979,9 @@ static int i915_getparam(struct drm_device *dev, void *data,
 	case I915_PARAM_HAS_VEBOX:
 		value = intel_ring_initialized(&dev_priv->ring[VECS]);
 		break;
+	case I915_PARAM_HAS_BSD2:
+		value = intel_ring_initialized(&dev_priv->ring[VCS2]);
+		break;
 	case I915_PARAM_HAS_RELAXED_FENCING:
 		value = 1;
 		break;
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index fcb16bf..fa99129 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -341,6 +341,7 @@ typedef struct drm_i915_irq_wait {
 #define I915_PARAM_HAS_WT     	 	 27
 #define I915_PARAM_CMD_PARSER_VERSION	 28
 #define I915_PARAM_HAS_COHERENT_PHYS_GTT 29
+#define I915_PARAM_HAS_BSD2		 30
 
 typedef struct drm_i915_getparam {
 	int param;
-- 
1.9.3

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Re: [PATCH 3/8] drm/i915: add I915_PARAM_HAS_BSD2 to i915_getparam

[Rodrigo Vivi]

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

On Mon, Nov 10, 2014 at 4:52 AM, Rodrigo Vivi <rodrigo.vivi@intel.com> wrote:
> From: Zhipeng Gong <zhipeng.gong@intel.com>
>
> This will let userland only try to use the new ring
> when the appropriate kernel is present
>
> Signed-off-by: Zhipeng Gong <zhipeng.gong@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_dma.c | 3 +++
>  include/uapi/drm/i915_drm.h     | 1 +
>  2 files changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
> index 5dc37f0..1c145ed 100644
> --- a/drivers/gpu/drm/i915/i915_dma.c
> +++ b/drivers/gpu/drm/i915/i915_dma.c
> @@ -979,6 +979,9 @@ static int i915_getparam(struct drm_device *dev, void *data,
>         case I915_PARAM_HAS_VEBOX:
>                 value = intel_ring_initialized(&dev_priv->ring[VECS]);
>                 break;
> +       case I915_PARAM_HAS_BSD2:
> +               value = intel_ring_initialized(&dev_priv->ring[VCS2]);
> +               break;
>         case I915_PARAM_HAS_RELAXED_FENCING:
>                 value = 1;
>                 break;
> diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> index fcb16bf..fa99129 100644
> --- a/include/uapi/drm/i915_drm.h
> +++ b/include/uapi/drm/i915_drm.h
> @@ -341,6 +341,7 @@ typedef struct drm_i915_irq_wait {
>  #define I915_PARAM_HAS_WT               27
>  #define I915_PARAM_CMD_PARSER_VERSION   28
>  #define I915_PARAM_HAS_COHERENT_PHYS_GTT 29
> +#define I915_PARAM_HAS_BSD2             30
>
>  typedef struct drm_i915_getparam {
>         int param;
> --
> 1.9.3
>
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
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[PATCH 4/8] drm/i915: Move the ban period onto the context

[Rodrigo Vivi]

From: Chris Wilson <chris@chris-wilson.co.uk>

This will allow us to set per-file, or even per-context, periods in the
future.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h         | 5 +++++
 drivers/gpu/drm/i915/i915_gem.c         | 3 ++-
 drivers/gpu/drm/i915/i915_gem_context.c | 2 ++
 3 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 1219282..cddecaf 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -622,6 +622,11 @@ struct i915_ctx_hang_stats {
 	/* Time when this context was last blamed for a GPU reset */
 	unsigned long guilty_ts;
 
+	/* If the contexts causes a second GPU hang within this time,
+	 * it is permanently banned from submitting any more work.
+	 */
+	unsigned long ban_period_seconds;
+
 	/* This context is banned to submit more work */
 	bool banned;
 };
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 86cf428..2eb66a6 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2540,7 +2540,8 @@ static bool i915_context_is_banned(struct drm_i915_private *dev_priv,
 	if (ctx->hang_stats.banned)
 		return true;
 
-	if (elapsed <= DRM_I915_CTX_BAN_PERIOD) {
+	if (ctx->hang_stats.ban_period_seconds &&
+	    elapsed <= ctx->hang_stats.ban_period_seconds) {
 		if (!i915_gem_context_is_default(ctx)) {
 			DRM_DEBUG("context hanging too fast, banning!\n");
 			return true;
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
index 7d32571..29150a4 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -219,6 +219,8 @@ __create_hw_context(struct drm_device *dev,
 	 * is no remap info, it will be a NOP. */
 	ctx->remap_slice = (1 << NUM_L3_SLICES(dev)) - 1;
 
+	ctx->hang_stats.ban_period_seconds = DRM_I915_CTX_BAN_PERIOD;
+
 	return ctx;
 
 err_out:
-- 
1.9.3

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[PATCH 5/8] drm/i915: Add ioctl to set per-context parameters

[Rodrigo Vivi]

From: Chris Wilson <chris@chris-wilson.co.uk>

Sometimes we wish to tweak how an individual context behaves. Since we
always create a context for every filp, this means that individual
processes can fine tune their behaviour even if they do not explicitly
create a context.

The first example parameter here is to enable multi-process GPU testing,
but the interface should be able to cope with passing arbitrarily complex
parameters.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/i915_dma.c         |  2 +
 drivers/gpu/drm/i915/i915_drv.h         |  4 ++
 drivers/gpu/drm/i915/i915_gem_context.c | 69 +++++++++++++++++++++++++++++++++
 include/uapi/drm/i915_drm.h             | 12 ++++++
 4 files changed, 87 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 1c145ed..04a6f77 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -2042,6 +2042,8 @@ const struct drm_ioctl_desc i915_ioctls[] = {
 	DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
 	DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_get_reset_stats_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
 	DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
+	DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
+	DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
 };
 
 int i915_max_ioctl = ARRAY_SIZE(i915_ioctls);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index cddecaf..6d99ddf 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2749,6 +2749,10 @@ int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
 				  struct drm_file *file);
 int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
 				   struct drm_file *file);
+int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data,
+				    struct drm_file *file_priv);
+int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data,
+				    struct drm_file *file_priv);
 
 /* i915_gem_evict.c */
 int __must_check i915_gem_evict_something(struct drm_device *dev,
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
index 29150a4..15c1602 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -743,3 +743,72 @@ int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
 	DRM_DEBUG_DRIVER("HW context %d destroyed\n", args->ctx_id);
 	return 0;
 }
+
+int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data,
+				    struct drm_file *file)
+{
+	struct drm_i915_file_private *file_priv = file->driver_priv;
+	struct drm_i915_gem_context_param *args = data;
+	struct intel_context *ctx;
+	int ret;
+
+	ret = i915_mutex_lock_interruptible(dev);
+	if (ret)
+		return ret;
+
+	ctx = i915_gem_context_get(file_priv, args->ctx_id);
+	if (IS_ERR(ctx)) {
+		mutex_unlock(&dev->struct_mutex);
+		return PTR_ERR(ctx);
+	}
+
+	args->size = 0;
+	switch (args->param) {
+	case I915_CONTEXT_PARAM_BAN_PERIOD:
+		args->value = ctx->hang_stats.ban_period_seconds;
+		break;
+	default:
+		ret = -EINVAL;
+		break;
+	}
+	mutex_unlock(&dev->struct_mutex);
+
+	return ret;
+}
+
+int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data,
+				    struct drm_file *file)
+{
+	struct drm_i915_file_private *file_priv = file->driver_priv;
+	struct drm_i915_gem_context_param *args = data;
+	struct intel_context *ctx;
+	int ret;
+
+	ret = i915_mutex_lock_interruptible(dev);
+	if (ret)
+		return ret;
+
+	ctx = i915_gem_context_get(file_priv, args->ctx_id);
+	if (IS_ERR(ctx)) {
+		mutex_unlock(&dev->struct_mutex);
+		return PTR_ERR(ctx);
+	}
+
+	switch (args->param) {
+	case I915_CONTEXT_PARAM_BAN_PERIOD:
+		if (args->size)
+			ret = -EINVAL;
+		else if (args->value < ctx->hang_stats.ban_period_seconds &&
+			 !capable(CAP_SYS_ADMIN))
+			ret = -EPERM;
+		else
+			ctx->hang_stats.ban_period_seconds = args->value;
+		break;
+	default:
+		ret = -EINVAL;
+		break;
+	}
+	mutex_unlock(&dev->struct_mutex);
+
+	return ret;
+}
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index fa99129..d253c85 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -224,6 +224,8 @@ typedef struct _drm_i915_sarea {
 #define DRM_I915_REG_READ		0x31
 #define DRM_I915_GET_RESET_STATS	0x32
 #define DRM_I915_GEM_USERPTR		0x33
+#define DRM_I915_GEM_CONTEXT_GETPARAM	0x34
+#define DRM_I915_GEM_CONTEXT_SETPARAM	0x35
 
 #define DRM_IOCTL_I915_INIT		DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
 #define DRM_IOCTL_I915_FLUSH		DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
@@ -275,6 +277,8 @@ typedef struct _drm_i915_sarea {
 #define DRM_IOCTL_I915_REG_READ			DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read)
 #define DRM_IOCTL_I915_GET_RESET_STATS		DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GET_RESET_STATS, struct drm_i915_reset_stats)
 #define DRM_IOCTL_I915_GEM_USERPTR			DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_USERPTR, struct drm_i915_gem_userptr)
+#define DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM	DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_GETPARAM, struct drm_i915_gem_context_param)
+#define DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM	DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_SETPARAM, struct drm_i915_gem_context_param)
 
 /* Allow drivers to submit batchbuffers directly to hardware, relying
  * on the security mechanisms provided by hardware.
@@ -1080,4 +1084,12 @@ struct drm_i915_gem_userptr {
 	__u32 handle;
 };
 
+struct drm_i915_gem_context_param {
+	__u32 ctx_id;
+	__u32 size;
+	__u64 param;
+#define I915_CONTEXT_PARAM_BAN_PERIOD 0x1
+	__u64 value;
+};
+
 #endif /* _UAPI_I915_DRM_H_ */
-- 
1.9.3

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[PATCH 6/8] drm/i915: Put logical pipe_control emission into a helper.

[Rodrigo Vivi]

To be used for a Workaroud. Similar to:

commit 884ceacee308f0e4616d0c933518af2639f7b1d8
Author: Kenneth Graunke <kenneth@whitecape.org>
Date:   Sat Jun 28 02:04:20 2014 +0300

    drm/i915: Refactor Broadwell PIPE_CONTROL emission into a helper.

Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/intel_lrc.c | 35 +++++++++++++++++++++--------------
 1 file changed, 21 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 6025ac7..666c000 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1126,6 +1126,26 @@ static int gen8_emit_flush(struct intel_ringbuffer *ringbuf,
 	return 0;
 }
 
+static int gen8_emit_pipe_control(struct intel_ringbuffer *ringbuf,
+				  u32 flags, u32 scratch_addr)
+{
+	int ret;
+
+	ret = intel_logical_ring_begin(ringbuf, 6);
+	if (ret)
+		return ret;
+
+	intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6));
+	intel_logical_ring_emit(ringbuf, flags);
+	intel_logical_ring_emit(ringbuf, scratch_addr);
+	intel_logical_ring_emit(ringbuf, 0);
+	intel_logical_ring_emit(ringbuf, 0);
+	intel_logical_ring_emit(ringbuf, 0);
+	intel_logical_ring_advance(ringbuf);
+
+	return 0;
+}
+
 static int gen8_emit_flush_render(struct intel_ringbuffer *ringbuf,
 				  u32 invalidate_domains,
 				  u32 flush_domains)
@@ -1133,7 +1153,6 @@ static int gen8_emit_flush_render(struct intel_ringbuffer *ringbuf,
 	struct intel_engine_cs *ring = ringbuf->ring;
 	u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 	u32 flags = 0;
-	int ret;
 
 	flags |= PIPE_CONTROL_CS_STALL;
 
@@ -1153,19 +1172,7 @@ static int gen8_emit_flush_render(struct intel_ringbuffer *ringbuf,
 		flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
 	}
 
-	ret = intel_logical_ring_begin(ringbuf, 6);
-	if (ret)
-		return ret;
-
-	intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6));
-	intel_logical_ring_emit(ringbuf, flags);
-	intel_logical_ring_emit(ringbuf, scratch_addr);
-	intel_logical_ring_emit(ringbuf, 0);
-	intel_logical_ring_emit(ringbuf, 0);
-	intel_logical_ring_emit(ringbuf, 0);
-	intel_logical_ring_advance(ringbuf);
-
-	return 0;
+	return gen8_emit_pipe_control(ringbuf, flags, scratch_addr);
 }
 
 static u32 gen8_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
-- 
1.9.3

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[PATCH 7/8] drm/i915: Add WaCsStallBeforeStateCacheInvalidate:bdw, chv to logical ring

[Rodrigo Vivi]

Similar to:

commit 02c9f7e3cfe76a7f54ef03438c36aade86cc1c8b
Author: Kenneth Graunke <kenneth@whitecape.org>
Date:   Mon Jan 27 14:20:16 2014 -0800

    drm/i915: Add the WaCsStallBeforeStateCacheInvalidate:bdw workaround.

    On Broadwell, any PIPE_CONTROL with the "State Cache Invalidate" bit set
    must be preceded by a PIPE_CONTROL with the "CS Stall" bit set.

    Documented on the BSpec 3D workarounds page.

Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/intel_lrc.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 666c000..54bf724 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1153,6 +1153,7 @@ static int gen8_emit_flush_render(struct intel_ringbuffer *ringbuf,
 	struct intel_engine_cs *ring = ringbuf->ring;
 	u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 	u32 flags = 0;
+	int ret;
 
 	flags |= PIPE_CONTROL_CS_STALL;
 
@@ -1170,6 +1171,15 @@ static int gen8_emit_flush_render(struct intel_ringbuffer *ringbuf,
 		flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 		flags |= PIPE_CONTROL_QW_WRITE;
 		flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
+
+
+		/* WaCsStallBeforeStateCacheInvalidate:bdw,chv */
+		ret = gen8_emit_pipe_control(ring,
+					     PIPE_CONTROL_CS_STALL |
+					     PIPE_CONTROL_STALL_AT_SCOREBOARD,
+					     0);
+		if (ret)
+			return ret;
 	}
 
 	return gen8_emit_pipe_control(ringbuf, flags, scratch_addr);
-- 
1.9.3

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[PATCH 8/8] drm/i915: Wait thread status on gen8+ fw sequence

[Rodrigo Vivi]

From: Mika Kuoppala <mika.kuoppala@linux.intel.com>

As per latest pm guide, we need to do this also on
past hsw.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/intel_uncore.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 6a0c3fb..86a755a 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -120,8 +120,7 @@ static void __gen7_gt_force_wake_mt_get(struct drm_i915_private *dev_priv,
 		DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
 
 	/* WaRsForcewakeWaitTC0:ivb,hsw */
-	if (INTEL_INFO(dev_priv->dev)->gen < 8)
-		__gen6_gt_wait_for_thread_c0(dev_priv);
+	__gen6_gt_wait_for_thread_c0(dev_priv);
 }
 
 static void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)
-- 
1.9.3

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Re: [PATCH 8/8] drm/i915: Wait thread status on gen8+ fw

[shuang.he]

Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
-------------------------------------Summary-------------------------------------
Platform: baseline_drm_intel_nightly_pass_rate->patch_applied_pass_rate
BYT: pass/total=247/348->275/348
PNV: pass/total=326/328->323/328
ILK: pass/total=329/330->329/330
IVB: pass/total=544/546->544/546
SNB: pass/total=556/561->556/561
HSW: pass/total=300/301->299/301
BDW: pass/total=435/435->433/435
-------------------------------------Detailed-------------------------------------
test_platform: test_suite, test_case, result_with_drm_intel_nightly(count, machine_id...)...->result_with_patch_applied(count, machine_id)...
BYT: Intel_gpu_tools, igt_drv_hangman_error-state-basic, INIT(1, M31)PASS(12, M31M36M29M38) -> PASS(4, M29)
BYT: Intel_gpu_tools, igt_drv_hangman_error-state-capture-blt, INIT(1, M31)PASS(9, M31M36M29) -> PASS(4, M29)
BYT: Intel_gpu_tools, igt_drv_hangman_error-state-capture-bsd, INIT(1, M31)PASS(9, M31M36M29) -> PASS(4, M29)
BYT: Intel_gpu_tools, igt_drv_hangman_error-state-capture-render, INIT(1, M31)PASS(9, M31M36M29) -> PASS(4, M29)
BYT: Intel_gpu_tools, igt_drv_hangman_error-state-debugfs-entry, INIT(1, M31)PASS(9, M31M36M29) -> PASS(4, M29)
BYT: Intel_gpu_tools, igt_drv_hangman_error-state-sysfs-entry, INIT(1, M31)PASS(9, M31M36M29) -> PASS(4, M29)
BYT: Intel_gpu_tools, igt_gem_bad_reloc_negative-reloc-lut, PASS(4, M31M29) -> NSPT(1, M29)PASS(3, M29)
BYT: Intel_gpu_tools, igt_gem_exec_params_invalid-flag, FAIL(3, M29)PASS(1, M31) -> FAIL(1, M29)PASS(3, M29)
BYT: Intel_gpu_tools, igt_gem_reset_stats_ban-ctx-render, INIT(1, M31)PASS(9, M31M36M29) -> PASS(4, M29)
BYT: Intel_gpu_tools, igt_gem_reset_stats_ban-render, INIT(1, M31)PASS(9, M31M36M29) -> PASS(4, M29)
BYT: Intel_gpu_tools, igt_gem_reset_stats_close-pending-blt, INIT(1, M31)DMESG_WARN(7, M31M36M29)PASS(2, M31M36) -> DMESG_WARN(3, M29)PASS(1, M29)
BYT: Intel_gpu_tools, igt_gem_reset_stats_close-pending-bsd, INIT(1, M31)DMESG_WARN(5, M36M29)PASS(4, M31M29) -> DMESG_WARN(2, M29)PASS(2, M29)
BYT: Intel_gpu_tools, igt_gem_reset_stats_close-pending-ctx-render, INIT(1, M31)PASS(9, M31M36M29) -> PASS(4, M29)
BYT: Intel_gpu_tools, igt_gem_reset_stats_close-pending-fork-blt, INIT(1, M31)DMESG_WARN(5, M31M36M29)PASS(4, M31M36M29) -> DMESG_WARN(2, M29)PASS(2, M29)
BYT: Intel_gpu_tools, igt_gem_reset_stats_close-pending-fork-bsd, INIT(1, M31)DMESG_WARN(5, M31M36M29)PASS(4, M31M36M29) -> DMESG_WARN(2, M29)PASS(2, M29)
BYT: Intel_gpu_tools, igt_gem_reset_stats_close-pending-fork-render, INIT(1, M31)PASS(9, M31M36M29) -> PASS(4, M29)
BYT: Intel_gpu_tools, igt_gem_reset_stats_close-pending-fork-reverse-blt, INIT(1, M31)PASS(9, M31M36M29) -> PASS(4, M29)
BYT: Intel_gpu_tools, igt_gem_reset_stats_close-pending-fork-reverse-bsd, INIT(1, M31)PASS(9, M31M36M29) -> PASS(4, M29)
BYT: Intel_gpu_tools, igt_gem_reset_stats_close-pending-fork-reverse-render, INIT(1, M31)PASS(9, M31M36M29) -> PASS(4, M29)
BYT: Intel_gpu_tools, igt_gem_reset_stats_close-pending-render, INIT(1, M31)PASS(9, M31M36M29) -> PASS(4, M29)
BYT: Intel_gpu_tools, igt_gem_reset_stats_params, INIT(1, M31)PASS(9, M31M36M29) -> PASS(4, M29)
BYT: Intel_gpu_tools, igt_gem_reset_stats_params-ctx-render, INIT(1, M31)PASS(9, M31M36M29) -> PASS(4, M29)
BYT: Intel_gpu_tools, igt_gem_reset_stats_reset-count-blt, INIT(1, M31)DMESG_WARN(8, M31M36M29)PASS(1, M29) -> PASS(4, M29)
BYT: Intel_gpu_tools, igt_gem_reset_stats_reset-count-bsd, INIT(1, M31)DMESG_WARN(7, M31M36M29)PASS(2, M36) -> DMESG_WARN(3, M29)PASS(1, M29)
BYT: Intel_gpu_tools, igt_gem_reset_stats_reset-count-ctx-render, INIT(1, M31)PASS(9, M31M36M29) -> PASS(4, M29)
BYT: Intel_gpu_tools, igt_gem_reset_stats_reset-count-render, INIT(1, M31)PASS(9, M31M36M29) -> PASS(4, M29)
BYT: Intel_gpu_tools, igt_gem_reset_stats_reset-stats-blt, INIT(1, M31)DMESG_WARN(3, M36M29)PASS(6, M31M36M29) -> DMESG_WARN(2, M29)PASS(2, M29)
BYT: Intel_gpu_tools, igt_gem_reset_stats_reset-stats-bsd, INIT(1, M31)DMESG_WARN(4, M36M29)PASS(5, M31M36M29) -> DMESG_WARN(2, M29)PASS(2, M29)
BYT: Intel_gpu_tools, igt_gem_reset_stats_reset-stats-ctx-render, INIT(1, M31)PASS(9, M31M36M29) -> PASS(4, M29)
BYT: Intel_gpu_tools, igt_gem_reset_stats_reset-stats-render, INIT(1, M31)PASS(9, M31M36M29) -> PASS(4, M29)
BYT: Intel_gpu_tools, igt_gem_reset_stats_unrelated-ctx-render, INIT(1, M31)PASS(9, M31M36M29) -> PASS(4, M29)
BYT: Intel_gpu_tools, igt_drv_hangman_ring-stop-sysfs-entry, INIT(1, M31)PASS(9, M31M36M29) -> PASS(4, M29)
PNV: Intel_gpu_tools, igt_drv_hangman_error-state-basic, PASS(4, M25M23) -> DMESG_WARN(1, M23)PASS(3, M23)
PNV: Intel_gpu_tools, igt_gem_exec_params_invalid-flag, FAIL(3, M23)PASS(1, M25) -> FAIL(1, M23)PASS(3, M23)
PNV: Intel_gpu_tools, igt_gem_linear_blits_normal, NSPT(6, M23M7)PASS(1, M25) -> NSPT(4, M23)
ILK: Intel_gpu_tools, igt_gem_exec_params_invalid-flag, FAIL(3, M37)PASS(1, M26) -> FAIL(1, M37)PASS(3, M37)
ILK: Intel_gpu_tools, igt_kms_flip_flip-vs-modeset-interruptible, DMESG_WARN(1, M26)PASS(9, M37) -> PASS(4, M37)
IVB: Intel_gpu_tools, igt_gem_exec_params_invalid-flag, FAIL(3, M21)PASS(1, M34) -> FAIL(1, M21)PASS(3, M21)
IVB: Intel_gpu_tools, igt_kms_plane_plane-position-covered-pipe-A-plane-1, TIMEOUT(1, M34)PASS(3, M21) -> PASS(4, M21)
SNB: Intel_gpu_tools, igt_gem_exec_params_invalid-flag, FAIL(3, M35)PASS(1, M35) -> FAIL(1, M35)PASS(3, M35)
SNB: Intel_gpu_tools, igt_kms_cursor_crc_cursor-256x256-sliding, DMESG_WARN(1, M35)PASS(3, M35) -> PASS(4, M35)
HSW: Intel_gpu_tools, igt_gem_exec_params_invalid-flag, PASS(1, M40) -> FAIL(1, M19)
BDW: Intel_gpu_tools, igt_gem_exec_params_invalid-flag, FAIL(3, M30)PASS(1, M42) -> FAIL(1, M30)PASS(3, M30)
BDW: Intel_gpu_tools, igt_gem_reset_stats_ban-bsd, PASS(10, M42M30M28) -> DMESG_WARN(1, M30)PASS(3, M30)
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Re: [PATCH 8/8] drm/i915: Wait thread status on gen8+ fw sequence

[Ville Syrjälä]

On Mon, Nov 10, 2014 at 04:52:50AM -0800, Rodrigo Vivi wrote:
> From: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> 
> As per latest pm guide, we need to do this also on
> past hsw.

Yep, matches the doc.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

BTW I wonder why we also wait for the [18:16] bits to clear on HSW? I don't
see such a thing documented in the HSW PM guide I have here. Maybe we can
just drop the HSW special case?

Also I wonder if we want this on CHV too. I should probably know, but I
dont't. I'll go bash some registers and see what they say...

> 
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Damien Lespiau <damien.lespiau@intel.com>
> Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_uncore.c | 3 +--
>  1 file changed, 1 insertion(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> index 6a0c3fb..86a755a 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -120,8 +120,7 @@ static void __gen7_gt_force_wake_mt_get(struct drm_i915_private *dev_priv,
>  		DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
>  
>  	/* WaRsForcewakeWaitTC0:ivb,hsw */
> -	if (INTEL_INFO(dev_priv->dev)->gen < 8)
> -		__gen6_gt_wait_for_thread_c0(dev_priv);
> +	__gen6_gt_wait_for_thread_c0(dev_priv);
>  }
>  
>  static void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)
> -- 
> 1.9.3

-- 
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Intel OTC
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Re: [PATCH 8/8] drm/i915: Wait thread status on gen8+ fw sequence

[Ville Syrjälä]

On Tue, Nov 11, 2014 at 07:12:29PM +0200, Ville Syrjälä wrote:
> On Mon, Nov 10, 2014 at 04:52:50AM -0800, Rodrigo Vivi wrote:
> > From: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> > 
> > As per latest pm guide, we need to do this also on
> > past hsw.
> 
> Yep, matches the doc.
> 
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> BTW I wonder why we also wait for the [18:16] bits to clear on HSW? I don't
> see such a thing documented in the HSW PM guide I have here. Maybe we can
> just drop the HSW special case?
> 
> Also I wonder if we want this on CHV too. I should probably know, but I
> dont't. I'll go bash some registers and see what they say...

So the register doesn't seem to exist on CHV. All I get is 0x0, no
matter if the GT is idle or busy. rc6 residency keeps ticking along
at a constant rate so it seems to be in rc6 when I tried this.

# ./intel_reg_read 0x13805c
0x13805C : 0x0
# IGT_NO_FORCEWAKE=1 ./intel_reg_read 0x13805c
0x13805C : 0x0

On IVB it clearly works:
# ./intel_reg_read 0x13805c
0x13805C : 0x40000000
# IGT_NO_FORCEWAKE=1 ./intel_reg_read 0x13805c
0x13805C : 0x30303

I think someone needs to try this on VLV too...

> 
> > 
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Cc: Chris Wilson <chris@chris-wilson.co.uk>
> > Cc: Damien Lespiau <damien.lespiau@intel.com>
> > Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_uncore.c | 3 +--
> >  1 file changed, 1 insertion(+), 2 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> > index 6a0c3fb..86a755a 100644
> > --- a/drivers/gpu/drm/i915/intel_uncore.c
> > +++ b/drivers/gpu/drm/i915/intel_uncore.c
> > @@ -120,8 +120,7 @@ static void __gen7_gt_force_wake_mt_get(struct drm_i915_private *dev_priv,
> >  		DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
> >  
> >  	/* WaRsForcewakeWaitTC0:ivb,hsw */
> > -	if (INTEL_INFO(dev_priv->dev)->gen < 8)
> > -		__gen6_gt_wait_for_thread_c0(dev_priv);
> > +	__gen6_gt_wait_for_thread_c0(dev_priv);
> >  }
> >  
> >  static void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)
> > -- 
> > 1.9.3
> 
> -- 
> Ville Syrjälä
> Intel OTC
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

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Re: [PATCH 8/8] drm/i915: Wait thread status on gen8+ fw sequence

[Daniel Vetter]

On Tue, Nov 11, 2014 at 07:12:29PM +0200, Ville Syrjälä wrote:
> On Mon, Nov 10, 2014 at 04:52:50AM -0800, Rodrigo Vivi wrote:
> > From: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> > 
> > As per latest pm guide, we need to do this also on
> > past hsw.
> 
> Yep, matches the doc.
> 
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Queued for -next, thanks for the patch.
> 
> BTW I wonder why we also wait for the [18:16] bits to clear on HSW? I don't
> see such a thing documented in the HSW PM guide I have here. Maybe we can
> just drop the HSW special case?

Iirc (commit message is silent unfortunately) this is for the GT3. And
since they're 0 on other hsw we've opted for a tricky silent gt3 enabling
by claiming this is for all of hsw. At least that's the story I remember.

No idea whether bdw gt3 would need this, too. Might be good to
double-check.
-Daniel
-- 
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+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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Re: [PATCH 8/8] drm/i915: Wait thread status on gen8+ fw sequence

[Ville Syrjälä]

On Wed, Nov 12, 2014 at 10:28:10AM +0100, Daniel Vetter wrote:
> On Tue, Nov 11, 2014 at 07:12:29PM +0200, Ville Syrjälä wrote:
> > On Mon, Nov 10, 2014 at 04:52:50AM -0800, Rodrigo Vivi wrote:
> > > From: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> > > 
> > > As per latest pm guide, we need to do this also on
> > > past hsw.
> > 
> > Yep, matches the doc.
> > 
> > Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Queued for -next, thanks for the patch.
> > 
> > BTW I wonder why we also wait for the [18:16] bits to clear on HSW? I don't
> > see such a thing documented in the HSW PM guide I have here. Maybe we can
> > just drop the HSW special case?
> 
> Iirc (commit message is silent unfortunately) this is for the GT3. And
> since they're 0 on other hsw we've opted for a tricky silent gt3 enabling
> by claiming this is for all of hsw. At least that's the story I remember.
> 
> No idea whether bdw gt3 would need this, too. Might be good to
> double-check.

The docs claim these are the same old thread wish result bits ever since
snb.

I just tried intel_reg_read on hsw gt2 and gt3 and both give identical
results to ivb. So my hunch is that we can just drop the hsw special
case.

-- 
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