From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 74336C001DC for ; Mon, 17 Jul 2023 14:13:04 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 32F8110E262; Mon, 17 Jul 2023 14:13:03 +0000 (UTC) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTPS id 1791A10E260; Mon, 17 Jul 2023 14:12:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1689603180; x=1721139180; h=message-id:date:mime-version:subject:to:cc:references: from:in-reply-to; bh=nIH7TP/6GpxY5/i6QotmcWHkrE1acoCnIAiOb8nnQnM=; b=MFDADXk0gTPP5dRPQ5tAhfDImUN4vwJbmy2VSzmi17NwmOJaCMZh7O4v mw61BsTE/9M2gVoVIvgxYK6sCvjg2l2BKJsXta9b+FjihcDXbkOobDjIP nLpnjNtwAX4KaySgt8jpzi9RzF3grkUfxYwf8B4S7fpKagZLbWW9P8gQK 0q4XMA4JUfOCk7eCZP4AImP0g6+2xRhyU20UpfNPrjH8IefGMLL7TsHxj 7RhL1I/QUMV9dZXmVCmaryAPQP8bMr7BW+3rAVsOI6sohNkHJuajWXoHQ +5RNoDn+6FQqD8XRkmOEgGFO8NlLe2dRq2BqzqZMZ+9D1gCeJffxQ/3qh w==; X-IronPort-AV: E=McAfee;i="6600,9927,10774"; a="355876895" X-IronPort-AV: E=Sophos;i="6.01,211,1684825200"; d="scan'208,217";a="355876895" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Jul 2023 07:12:59 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10774"; a="673548334" X-IronPort-AV: E=Sophos;i="6.01,211,1684825200"; d="scan'208,217";a="673548334" Received: from nirmoyda-mobl.ger.corp.intel.com (HELO [10.249.36.7]) ([10.249.36.7]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Jul 2023 07:12:57 -0700 Content-Type: multipart/alternative; boundary="------------tB0gficugwiJT7m03dn2hHNh" Message-ID: Date: Mon, 17 Jul 2023 16:12:55 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.13.0 Content-Language: en-US To: Andi Shyti , Jonathan Cavitt , Matt Roper , Chris Wilson , Mika Kuoppala , Nirmoy Das References: <20230717125134.399115-1-andi.shyti@linux.intel.com> <20230717125134.399115-3-andi.shyti@linux.intel.com> From: Nirmoy Das In-Reply-To: <20230717125134.399115-3-andi.shyti@linux.intel.com> Subject: Re: [Intel-gfx] [PATCH v3 2/5] drm/i915/gt: Ensure memory quiesced before invalidation X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Intel GFX , DRI Devel Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" This is a multi-part message in MIME format. --------------tB0gficugwiJT7m03dn2hHNh Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 7/17/2023 2:51 PM, Andi Shyti wrote: > From: Jonathan Cavitt > > All memory traffic must be quiesced before requesting > an aux invalidation on platforms that use Aux CCS. > > Fixes: 972282c4cf24 ("drm/i915/gen12: Add aux table invalidate for all engines") > Signed-off-by: Jonathan Cavitt > Signed-off-by: Andi Shyti > Cc: # v5.8+ |Reviewed-by: Nirmoy Das | > --- > drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c > index 563efee055602..bee3b7dc595cf 100644 > --- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c > +++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c > @@ -202,6 +202,13 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode) > { > struct intel_engine_cs *engine = rq->engine; > > + /* > + * Aux invalidations on Aux CCS platforms require > + * memory traffic is quiesced prior. > + */ > + if ((mode & EMIT_INVALIDATE) && !HAS_FLAT_CCS(engine->i915)) > + mode |= EMIT_FLUSH; > + > if (mode & EMIT_FLUSH) { > u32 flags = 0; > int err; --------------tB0gficugwiJT7m03dn2hHNh Content-Type: text/html; charset=UTF-8 Content-Transfer-Encoding: 7bit


On 7/17/2023 2:51 PM, Andi Shyti wrote:
From: Jonathan Cavitt <jonathan.cavitt@intel.com>

All memory traffic must be quiesced before requesting
an aux invalidation on platforms that use Aux CCS.

Fixes: 972282c4cf24 ("drm/i915/gen12: Add aux table invalidate for all engines")
Signed-off-by: Jonathan Cavitt <jonathan.cavitt@intel.com>
Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
Cc: <stable@vger.kernel.org> # v5.8+

Reviewed-by: Nirmoy Das <nirmoy.das@intel.com>
---
 drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
index 563efee055602..bee3b7dc595cf 100644
--- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
@@ -202,6 +202,13 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode)
 {
 	struct intel_engine_cs *engine = rq->engine;
 
+	/*
+	 * Aux invalidations on Aux CCS platforms require
+	 * memory traffic is quiesced prior.
+	 */
+	if ((mode & EMIT_INVALIDATE) && !HAS_FLAT_CCS(engine->i915))
+		mode |= EMIT_FLUSH;
+
 	if (mode & EMIT_FLUSH) {
 		u32 flags = 0;
 		int err;
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