From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 67D72CA0FED for ; Wed, 27 Aug 2025 11:41:47 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E9D4610E7DE; Wed, 27 Aug 2025 11:41:46 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="WHfe3YXl"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.11]) by gabe.freedesktop.org (Postfix) with ESMTPS id E287910E7E6 for ; Wed, 27 Aug 2025 11:41:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1756294905; x=1787830905; h=from:to:subject:in-reply-to:references:date:message-id: mime-version; bh=udVoQTdkTcXIeNYGkLzg9TZjGXCs2NY3sd/JwstbJuU=; b=WHfe3YXlIhM5B+TCPD1MhcrvLWhu9rFaDWFRBKiBJzjNR7uFSan6Qwwo joLDNOJyj7feWp/TBbCBd4/bRlImNm5Rc/pzX4JJfACBxjMWCpIjOVTCP sdNFEm75NVXuxQkQUfRYik30rdhGjgoAkt3fpSbXcwqFjlLOw+uzRnvku r2RXMU1LPx1bkH/3goczem1ZxlbcSBeropaUZuV7NwA9Y747UHxjiNMCe BOj2gX3PzmVh4EOxW4K/8b3jf9dn86pm2O9xvXuv33Xc47VDZlRaDh1Os j3qv4Xiq/tY0XkYvf73gvzhG92bzM96zHZ9VxBTAoAbbi35cp+GNcVBna w==; X-CSE-ConnectionGUID: iK8nsbCTSJe0l+BeLY+CTA== X-CSE-MsgGUID: mYcv+F6oQ86mJlCiSvDG9w== X-IronPort-AV: E=McAfee;i="6800,10657,11534"; a="68814513" X-IronPort-AV: E=Sophos;i="6.18,214,1751266800"; d="scan'208";a="68814513" Received: from orviesa005.jf.intel.com ([10.64.159.145]) by orvoesa103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Aug 2025 04:41:43 -0700 X-CSE-ConnectionGUID: c2ZSD6xxRWO0EeNNOim9+A== X-CSE-MsgGUID: usp09K0fSwqPJGgjFzMBug== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.18,214,1751266800"; d="scan'208";a="175119857" Received: from hrotuna-mobl2.ger.corp.intel.com (HELO localhost) ([10.245.246.190]) by orviesa005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Aug 2025 04:41:41 -0700 From: Jani Nikula To: Luca Coelho , intel-gfx@lists.freedesktop.org Subject: Re: [PATCH v2] drm/i915: use REG_BIT on FW_BLC_SELF_* macros In-Reply-To: <20250827111109.401604-1-luciano.coelho@intel.com> Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo References: <20250827111109.401604-1-luciano.coelho@intel.com> Date: Wed, 27 Aug 2025 14:41:38 +0300 Message-ID: MIME-Version: 1.0 Content-Type: text/plain X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Wed, 27 Aug 2025, Luca Coelho wrote: > Use REG_BIT() instead of open coding the shift in the FW_BLC_SELF_* > macro definitions to avoid potentially typing them as 'int'. > > For example, this happens when we pass them to _MASKED_BIT_ENABLE(), > because of the typeof() construct there. When we pass 1 << 15 (the > FW_BLC_SELF_EN macro), we get typeof(1 << 15), which is 'int'. Then > the value becomes negative (-2147450880) and we try to assign it to a > 'u32'. > > In practice this is not a problem though, because when we try to > assign -2147450880 to the u32, that becomes 0x80008000, which was the > intended result. > > Signed-off-by: Luca Coelho Reviewed-by: Jani Nikula > --- > > In v2: > * changed to use REG_BIT() instead (Jani) > > > drivers/gpu/drm/i915/i915_reg.h | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index b283b25d8368..b4188e94c9a2 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -412,9 +412,9 @@ > #define FW_BLC _MMIO(0x20d8) > #define FW_BLC2 _MMIO(0x20dc) > #define FW_BLC_SELF _MMIO(0x20e0) /* 915+ only */ > -#define FW_BLC_SELF_EN_MASK (1 << 31) > -#define FW_BLC_SELF_FIFO_MASK (1 << 16) /* 945 only */ > -#define FW_BLC_SELF_EN (1 << 15) /* 945 only */ > +#define FW_BLC_SELF_EN_MASK REG_BIT((31) > +#define FW_BLC_SELF_FIFO_MASK REG_BIT(16) /* 945 only */ > +#define FW_BLC_SELF_EN REG_BIT(15) /* 945 only */ > #define MM_BURST_LENGTH 0x00700000 > #define MM_FIFO_WATERMARK 0x0001F000 > #define LM_BURST_LENGTH 0x00000700 -- Jani Nikula, Intel