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X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Feb 2024 10:04:03.0486 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: zscJQUaTByg/OXK5sc90dlmO4iBBH2Q3YrsbS0MtteBv2TJ7U+erBZyH0rd5U4my9K1qZelYwhgpDPBtY7VtuAMNq4ilHrsrwY/dC5gtcnw= X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR11MB7749 X-OriginatorOrg: intel.com X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On 2/22/2024 5:42 PM, Mitul Golani wrote: > Compute vrr_vsync_start/end which sets the position > for hardware to send the Vsync at a fixed position > relative to the end of the Vblank. > > --v2: > - Update, VSYNC_START/END macros to VRR_VSYNC_START/END.(Ankit) > - Update bit fields of VRR_VSYNC_START/END.(Ankit) > > Signed-off-by: Mitul Golani > --- > drivers/gpu/drm/i915/display/intel_display.c | 1 + > drivers/gpu/drm/i915/display/intel_display_types.h | 1 + > drivers/gpu/drm/i915/display/intel_vrr.c | 12 ++++++++++++ > drivers/gpu/drm/i915/i915_reg.h | 7 +++++++ > 4 files changed, 21 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > index 00ac65a14029..5994f7fcbb6a 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c > @@ -5321,6 +5321,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, > PIPE_CONF_CHECK_I(vrr.flipline); > PIPE_CONF_CHECK_I(vrr.pipeline_full); > PIPE_CONF_CHECK_I(vrr.guardband); > + PIPE_CONF_CHECK_BOOL(vrr.as_sdp_enable); Need to add PIPE_CONF_CHECK_I(vrr.vsync_start/end). > } > > #undef PIPE_CONF_CHECK_X > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h > index 93b4b7dff1d0..7859e4baad4b 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_types.h > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h > @@ -1416,6 +1416,7 @@ struct intel_crtc_state { > u16 flipline, vmin, vmax, guardband; > u8 as_sdp_mode; > bool as_sdp_enable; > + u32 vsync_end, vsync_start; > } vrr; > > /* Stream Splitter for eDP MSO */ > diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c > index 08e3ba69bd30..29ddf504d94b 100644 > --- a/drivers/gpu/drm/i915/display/intel_vrr.c > +++ b/drivers/gpu/drm/i915/display/intel_vrr.c > @@ -150,6 +150,13 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state, > > crtc_state->vrr.flipline = crtc_state->vrr.vmin + 1; > > + crtc_state->vrr.vsync_start = > + (crtc_state->hw.adjusted_mode.crtc_vtotal - > + VRR_VSYNC_START(crtc_state->hw.adjusted_mode.vsync_start)); > + crtc_state->vrr.vsync_end = > + (crtc_state->hw.adjusted_mode.crtc_vtotal - > + (VRR_VSYNC_END(crtc_state->hw.adjusted_mode.vsync_end) >> 16)); Need to add trans_vrr_start/end also in vrr_get_config. Make sure to read/write these only when we intend to send adaptive_sync sdp. Regards, Ankit > + > /* > * For XE_LPD+, we use guardband and pipeline override > * is deprecated. > @@ -273,8 +280,13 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state) > u32 trans_vrr_ctl; > > trans_vrr_ctl = intel_de_read(dev_priv, TRANS_VRR_CTL(cpu_transcoder)); > + bool as_sdp_enabled = > + intel_de_read(dev_priv, > + HSW_TVIDEO_DIP_CTL(cpu_transcoder)); > > crtc_state->vrr.enable = trans_vrr_ctl & VRR_CTL_VRR_ENABLE; > + crtc_state->vrr.as_sdp_enable = > + as_sdp_enabled & VIDEO_DIP_ENABLE_ADAPTIVE_SYNC; > > if (DISPLAY_VER(dev_priv) >= 13) > crtc_state->vrr.guardband = > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index c02ea07af4c2..3e0853458ef4 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -2007,7 +2007,9 @@ > #define _TRANS_VRR_CTL_B 0x61420 > #define _TRANS_VRR_CTL_C 0x62420 > #define _TRANS_VRR_CTL_D 0x63420 > +#define _TRANS_VRR_VSYNC_A 0x60078 > #define TRANS_VRR_CTL(trans) _MMIO_TRANS2(trans, _TRANS_VRR_CTL_A) > +#define TRANS_VRR_VSYNC(trans) _MMIO_TRANS2(trans, _TRANS_VRR_VSYNC_A) > #define VRR_CTL_VRR_ENABLE REG_BIT(31) > #define VRR_CTL_IGN_MAX_SHIFT REG_BIT(30) > #define VRR_CTL_FLIP_LINE_EN REG_BIT(29) > @@ -2087,6 +2089,11 @@ > #define TRANS_VRR_STATUS2(trans) _MMIO_TRANS2(trans, _TRANS_VRR_STATUS2_A) > #define VRR_STATUS2_VERT_LN_CNT_MASK REG_GENMASK(19, 0) > > +#define VRR_VSYNC_END_MASK REG_GENMASK(28, 16) > +#define VRR_VSYNC_END(vsync_end) REG_FIELD_PREP(VSYNC_END_MASK, (vsync_end)) > +#define VRR_VSYNC_START_MASK REG_GENMASK(12, 0) > +#define VRR_VSYNC_START(vsync_start) REG_FIELD_PREP(VSYNC_START_MASK, (vsync_start)) > + > #define _TRANS_PUSH_A 0x60A70 > #define _TRANS_PUSH_B 0x61A70 > #define _TRANS_PUSH_C 0x62A70