Re: [PATCH 09/13] drm/i915: don't use gtt_pwrite on LLC cached objects

Chris Wilson
2011-11-06T21:16:00Z

On Sun, 6 Nov 2011 20:13:56 +0100, Daniel Vetter <daniel.vetter@ffwll.ch> wrote:
> ~120 Âµs instead fo ~210 Âµs to write 1mb on my snb. I like this.
>
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> ---
> drivers/gpu/drm/i915/i915_gem.c | 1 +
> 1 files changed, 1 insertions(+), 0 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index 0048917..8fd175c 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -842,6 +842,7 @@ i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
> ret = i915_gem_phys_pwrite(dev, obj, args, file);
> goto out;
> } else if (obj->gtt_space &&
> + obj->cache_level == I915_CACHE_NONE &&
> obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
> ret = i915_gem_object_pin(obj, 0, true);
> if (ret)

I still think you want to include a obj->map_and_fenceable test here.
When doing 2D benchmarks the stall incurred here to evict an old object
map the to-be-written object into the mappable GTT causes measureable
pain (obviously on non-LLC architectures).

The series looks good and I'll look at the impact upon 2D for pnv and
snb over the next couple of days. With and without the extra check ;-)
-Chris

--
Chris Wilson, Intel Open Source Technology Centre