From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Souza, Jose" Subject: Re: [PATCH 4/5] drm/i915: Add PSR2 selective update status registers and bits definitions Date: Tue, 11 Dec 2018 14:20:07 +0000 Message-ID: References: <20181204230032.6352-1-jose.souza@intel.com> <20181204230032.6352-4-jose.souza@intel.com> <97444c13d54364c806f475c18d8317c65b06aeca.camel@intel.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============0557485906==" Return-path: Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTPS id AAC186E219 for ; Tue, 11 Dec 2018 14:20:09 +0000 (UTC) In-Reply-To: <97444c13d54364c806f475c18d8317c65b06aeca.camel@intel.com> Content-Language: en-US List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: "intel-gfx@lists.freedesktop.org" , "Pandiyan, Dhinakaran" Cc: "Vivi, Rodrigo" List-Id: intel-gfx@lists.freedesktop.org --===============0557485906== Content-Language: en-US Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="=-uCE5hY6k6iflyTkc+/m6" --=-uCE5hY6k6iflyTkc+/m6 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Mon, 2018-12-10 at 23:51 -0800, Dhinakaran Pandiyan wrote: > On Tue, 2018-12-04 at 15:00 -0800, Jos=C3=A9 Roberto de Souza wrote: > > This register contains how many blocks was sent in the past > > selective > > updates. > > Those registers are not kept set all the times but pulling it after > > flip > > can show that the expected values are set for the current frame and > > the > > previous ones too. > >=20 > > Cc: Rodrigo Vivi > > Cc: Dhinakaran Pandiyan > > Signed-off-by: Jos=C3=A9 Roberto de Souza > > --- > > drivers/gpu/drm/i915/i915_reg.h | 6 ++++++ > > 1 file changed, 6 insertions(+) > >=20 > > diff --git a/drivers/gpu/drm/i915/i915_reg.h > > b/drivers/gpu/drm/i915/i915_reg.h > > index 0a7d60509ca7..7d634f34ca7d 100644 > > --- a/drivers/gpu/drm/i915/i915_reg.h > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > @@ -4248,6 +4248,12 @@ enum { > > #define EDP_PSR2_STATUS_STATE_MASK (0xf << 28) > > #define EDP_PSR2_STATUS_STATE_SHIFT 28 > > =20 > > +#define EDP_PSR2_SU_STATUS _MMIO(0 > > x6f914) > > +#define EDP_PSR2_SU_STATUS2 =09 > > _MMIO(0 > > x6F918) > > +#define EDP_PSR2_SU_STATUS3 =09 > > _MMIO(0 > > x6F91C) > > +#define EDP_PSR2_SU_STATUS_NUM_SU_BLOCKS_IN_FRAME_SHIFT(i)=09 > > ((i) * > > 10) > > +#define EDP_PSR2_SU_STATUS_NUM_SU_BLOCKS_IN_FRAME_MASK(i) (0x3FF > > << ((i) * 10)) > How about moving the MMIO selection logic to the macros?=20 >=20 > #define PSR2_SU_HISTORY 8 > #define _PSR2_SU_STATUS_0 0x6f914 > #define _PSR2_SU_STATUS_1 0x6f918 > #define _PSR2_SU_STATUS(dword) _MMIO(_PICK_EVEN((dword),\ > _PSR2_SU_STATUS_0, _PSR2_SU_STATUS_1)) > #define PSR2_SU_SHIFT(frame) ((frame) % 3) * 10 > #define PSR2_SU_MASK(frame) (0x3ff << PSR2_SU_SHIFT(frame)) > #define PSR2_SU_BLOCKS(frame) _PSR2_SU_STATUS((frame) / 3) Looks better >=20 >=20 > > + > > /* VGA port control */ > > #define ADPA _MMIO(0x61100) > > #define PCH_ADPA _MMIO(0xe1100) --=-uCE5hY6k6iflyTkc+/m6 Content-Type: application/pgp-signature; name="signature.asc" Content-Description: This is a digitally signed message part Content-Transfer-Encoding: 7bit -----BEGIN PGP SIGNATURE----- iQEzBAABCAAdFiEEVNG051EijGa0MiaQVenbO/mOWkkFAlwPx5QACgkQVenbO/mO WkmFRQgAqAN4yPsr+qNm3iKSIUHILjwt6CrYIS/JIZ41xoiGe3nj3khuK0B0mtEz 2jVU2FbZewlg2MJwIpi+lGYNGU3ErFsIzxA9i2eHEwR9k8meGTGMJF01aaA4upqx DX0cymUPy/qVvP8yFI7aUnirbr2Jz3qz+uU0xi2rHeYumcDNY92D1GVxeM3vZRkG TbtreykHFWaCcVpC9qiU6W+bHxRKmGiXlraO72WTkjheJ0N5o2wnvrg0TV6B4/qC 1XHdsZfed5OkEc93n1Hxi70X7362xtQRfJGRkzEAf2ePuXi8YyXY00odarPkwXsT ftigB4InsDxexV5vUj3DQQJFcJtnew== =ofxE -----END PGP SIGNATURE----- --=-uCE5hY6k6iflyTkc+/m6-- --===============0557485906== Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Content-Disposition: inline X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KSW50ZWwtZ2Z4 IG1haWxpbmcgbGlzdApJbnRlbC1nZnhAbGlzdHMuZnJlZWRlc2t0b3Aub3JnCmh0dHBzOi8vbGlz dHMuZnJlZWRlc2t0b3Aub3JnL21haWxtYW4vbGlzdGluZm8vaW50ZWwtZ2Z4Cg== --===============0557485906==--