* [PATCH] drm/i915:gen9: Add WA for disable gather at set shader bit
@ 2015-08-07 17:33 Arun Siluvery
2015-08-08 5:35 ` Ben Widawsky
` (2 more replies)
0 siblings, 3 replies; 7+ messages in thread
From: Arun Siluvery @ 2015-08-07 17:33 UTC (permalink / raw)
To: intel-gfx; +Cc: Mika Kuoppala, Ben Widawsky
This WA doesn't have a name. According to the spec, driver need to reset
disable gather at set shader bit in per ctx WA batch. It is to be noted
that the default value is already '0' for this bit but we still need to
apply this WA because userspace may set it. If userspace really need it
to be set then they need to do in every batch.
Cc: Ben Widawsky <benjamin.widawsky@intel.com>
Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_lrc.c | 9 +++++++++
2 files changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ea46d68..838537f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5834,6 +5834,7 @@ enum skl_disp_power_wells {
# define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC ((1<<10) | (1<<26))
# define GEN9_RHWO_OPTIMIZATION_DISABLE (1<<14)
#define COMMON_SLICE_CHICKEN2 0x7014
+#define GEN9_DISABLE_GATHER_SET_SHADER_SLICE (1<<12)
# define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE (1<<0)
#define HIZ_CHICKEN 0x7018
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 4c40614..df3bb98 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1302,6 +1302,15 @@ static int gen9_init_perctx_bb(struct intel_engine_cs *ring,
struct drm_device *dev = ring->dev;
uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);
+ /* WaNoName:skl,bxt
+ * This WA has no name, according to the spec driver needs to reset
+ * "disable gather at set shader slice" bit in per ctx batch
+ */
+ wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1));
+ wa_ctx_emit(batch, index, COMMON_SLICE_CHICKEN2);
+ wa_ctx_emit(batch, index,
+ _MASKED_BIT_DISABLE(GEN9_DISABLE_GATHER_SET_SHADER_SLICE));
+
/* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
if ((IS_SKYLAKE(dev) && (INTEL_REVID(dev) <= SKL_REVID_B0)) ||
(IS_BROXTON(dev) && (INTEL_REVID(dev) == BXT_REVID_A0))) {
--
1.9.1
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http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH] drm/i915:gen9: Add WA for disable gather at set shader bit
2015-08-07 17:33 [PATCH] drm/i915:gen9: Add WA for disable gather at set shader bit Arun Siluvery
@ 2015-08-08 5:35 ` Ben Widawsky
2015-08-10 9:36 ` Siluvery, Arun
2015-08-12 13:34 ` [PATCH v2] " Arun Siluvery
2015-08-12 16:03 ` Arun Siluvery
2 siblings, 1 reply; 7+ messages in thread
From: Ben Widawsky @ 2015-08-08 5:35 UTC (permalink / raw)
To: Arun Siluvery; +Cc: intel-gfx, Sarah Sharp, Mika Kuoppala
On Fri, Aug 07, 2015 at 06:33:37PM +0100, Arun Siluvery wrote:
> This WA doesn't have a name. According to the spec, driver need to reset
> disable gather at set shader bit in per ctx WA batch. It is to be noted
> that the default value is already '0' for this bit but we still need to
> apply this WA because userspace may set it. If userspace really need it
> to be set then they need to do in every batch.
>
> Cc: Ben Widawsky <benjamin.widawsky@intel.com>
> Cc: Mika Kuoppala <mika.kuoppala@intel.com>
> Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/intel_lrc.c | 9 +++++++++
> 2 files changed, 10 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index ea46d68..838537f 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5834,6 +5834,7 @@ enum skl_disp_power_wells {
> # define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC ((1<<10) | (1<<26))
> # define GEN9_RHWO_OPTIMIZATION_DISABLE (1<<14)
> #define COMMON_SLICE_CHICKEN2 0x7014
> +#define GEN9_DISABLE_GATHER_SET_SHADER_SLICE (1<<12)
> # define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE (1<<0)
>
> #define HIZ_CHICKEN 0x7018
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index 4c40614..df3bb98 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -1302,6 +1302,15 @@ static int gen9_init_perctx_bb(struct intel_engine_cs *ring,
> struct drm_device *dev = ring->dev;
> uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);
>
> + /* WaNoName:skl,bxt
> + * This WA has no name, according to the spec driver needs to reset
> + * "disable gather at set shader slice" bit in per ctx batch
> + */
> + wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1));
> + wa_ctx_emit(batch, index, COMMON_SLICE_CHICKEN2);
> + wa_ctx_emit(batch, index,
> + _MASKED_BIT_DISABLE(GEN9_DISABLE_GATHER_SET_SHADER_SLICE));
> +
> /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
> if ((IS_SKYLAKE(dev) && (INTEL_REVID(dev) <= SKL_REVID_B0)) ||
> (IS_BROXTON(dev) && (INTEL_REVID(dev) == BXT_REVID_A0))) {
Hmm. I thought we needed this, but looking at the "User Mode Privileged
Commands" of the spec, it seems like this register is not allowed to be written.
So unless this register is put in a whitelist somewhere in the future, I think
it's safe to drop this patch.
As a preventative measure, I don't see this as harmful - but I don't feel I have
any authority to suggest whether we keep this in or not.
--
Ben Widawsky, Intel Open Source Technology Center
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http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH] drm/i915:gen9: Add WA for disable gather at set shader bit
2015-08-08 5:35 ` Ben Widawsky
@ 2015-08-10 9:36 ` Siluvery, Arun
0 siblings, 0 replies; 7+ messages in thread
From: Siluvery, Arun @ 2015-08-10 9:36 UTC (permalink / raw)
To: Ben Widawsky; +Cc: intel-gfx, Sarah Sharp, Mika Kuoppala
On 08/08/2015 06:35, Ben Widawsky wrote:
> On Fri, Aug 07, 2015 at 06:33:37PM +0100, Arun Siluvery wrote:
>> This WA doesn't have a name. According to the spec, driver need to reset
>> disable gather at set shader bit in per ctx WA batch. It is to be noted
>> that the default value is already '0' for this bit but we still need to
>> apply this WA because userspace may set it. If userspace really need it
>> to be set then they need to do in every batch.
>>
>> Cc: Ben Widawsky <benjamin.widawsky@intel.com>
>> Cc: Mika Kuoppala <mika.kuoppala@intel.com>
>> Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
>> ---
>> drivers/gpu/drm/i915/i915_reg.h | 1 +
>> drivers/gpu/drm/i915/intel_lrc.c | 9 +++++++++
>> 2 files changed, 10 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index ea46d68..838537f 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -5834,6 +5834,7 @@ enum skl_disp_power_wells {
>> # define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC ((1<<10) | (1<<26))
>> # define GEN9_RHWO_OPTIMIZATION_DISABLE (1<<14)
>> #define COMMON_SLICE_CHICKEN2 0x7014
>> +#define GEN9_DISABLE_GATHER_SET_SHADER_SLICE (1<<12)
>> # define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE (1<<0)
>>
>> #define HIZ_CHICKEN 0x7018
>> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
>> index 4c40614..df3bb98 100644
>> --- a/drivers/gpu/drm/i915/intel_lrc.c
>> +++ b/drivers/gpu/drm/i915/intel_lrc.c
>> @@ -1302,6 +1302,15 @@ static int gen9_init_perctx_bb(struct intel_engine_cs *ring,
>> struct drm_device *dev = ring->dev;
>> uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);
>>
>> + /* WaNoName:skl,bxt
>> + * This WA has no name, according to the spec driver needs to reset
>> + * "disable gather at set shader slice" bit in per ctx batch
>> + */
>> + wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1));
>> + wa_ctx_emit(batch, index, COMMON_SLICE_CHICKEN2);
>> + wa_ctx_emit(batch, index,
>> + _MASKED_BIT_DISABLE(GEN9_DISABLE_GATHER_SET_SHADER_SLICE));
>> +
>> /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
>> if ((IS_SKYLAKE(dev) && (INTEL_REVID(dev) <= SKL_REVID_B0)) ||
>> (IS_BROXTON(dev) && (INTEL_REVID(dev) == BXT_REVID_A0))) {
>
> Hmm. I thought we needed this, but looking at the "User Mode Privileged
> Commands" of the spec, it seems like this register is not allowed to be written.
> So unless this register is put in a whitelist somewhere in the future, I think
> it's safe to drop this patch.
We need to whitelist few registers for preemption related WA, this can
be added to whitelist if userspace really needs to write to it.
regards
Arun
>
> As a preventative measure, I don't see this as harmful - but I don't feel I have
> any authority to suggest whether we keep this in or not.
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH v2] drm/i915:gen9: Add WA for disable gather at set shader bit
2015-08-07 17:33 [PATCH] drm/i915:gen9: Add WA for disable gather at set shader bit Arun Siluvery
2015-08-08 5:35 ` Ben Widawsky
@ 2015-08-12 13:34 ` Arun Siluvery
2015-08-15 12:13 ` shuang.he
2015-08-12 16:03 ` Arun Siluvery
2 siblings, 1 reply; 7+ messages in thread
From: Arun Siluvery @ 2015-08-12 13:34 UTC (permalink / raw)
To: intel-gfx; +Cc: Mika Kuoppala, Ben Widawsky
This WA doesn't have a name. According to WA ID 0555 in spec, driver need to
reset disable gather at set shader bit in per ctx WA batch. It is to be noted
that the default value is already '0' for this bit but we still need to apply
this WA because userspace may set it. If userspace really need it to be set
then they need to do in every batch.
Cc: Ben Widawsky <benjamin.widawsky@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_lrc.c | 9 +++++++++
2 files changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7456bd2..d60a510 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5834,6 +5834,7 @@ enum skl_disp_power_wells {
# define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC ((1<<10) | (1<<26))
# define GEN9_RHWO_OPTIMIZATION_DISABLE (1<<14)
#define COMMON_SLICE_CHICKEN2 0x7014
+#define GEN9_DISABLE_GATHER_SET_SHADER_SLICE (1<<12)
# define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE (1<<0)
#define HIZ_CHICKEN 0x7018
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 5559ed9..e79be4c 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1305,6 +1305,15 @@ static int gen9_init_perctx_bb(struct intel_engine_cs *ring,
struct drm_device *dev = ring->dev;
uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);
+ /* WaNoName:skl,bxt
+ * This WA has no name, WA ID 0555 in spec says, driver needs to reset
+ * "disable gather at set shader slice" bit in per ctx batch
+ */
+ wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1));
+ wa_ctx_emit(batch, index, COMMON_SLICE_CHICKEN2);
+ wa_ctx_emit(batch, index,
+ _MASKED_BIT_DISABLE(GEN9_DISABLE_GATHER_SET_SHADER_SLICE));
+
/* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
if ((IS_SKYLAKE(dev) && (INTEL_REVID(dev) <= SKL_REVID_B0)) ||
(IS_BROXTON(dev) && (INTEL_REVID(dev) == BXT_REVID_A0))) {
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH v2] drm/i915:gen9: Add WA for disable gather at set shader bit
2015-08-07 17:33 [PATCH] drm/i915:gen9: Add WA for disable gather at set shader bit Arun Siluvery
2015-08-08 5:35 ` Ben Widawsky
2015-08-12 13:34 ` [PATCH v2] " Arun Siluvery
@ 2015-08-12 16:03 ` Arun Siluvery
2015-08-15 12:12 ` shuang.he
2 siblings, 1 reply; 7+ messages in thread
From: Arun Siluvery @ 2015-08-12 16:03 UTC (permalink / raw)
To: intel-gfx; +Cc: Mika Kuoppala, Ben Widawsky
This WA doesn't have a name. According to WA ID 0555 in spec, driver need to
reset disable gather at set shader bit in per ctx WA batch. It is to be noted
that the default value is already '0' for this bit but we still need to apply
this WA because userspace may set it. If userspace really need it to be set
then they need to do in every batch.
v2: include WA ID as there is no name (Joonas)
Cc: Ben Widawsky <benjamin.widawsky@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
---
This was already sent sometime back today but there was an error at my end,
sending it again to be sure. Also using this opportunity to add commit msg history.
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_lrc.c | 9 +++++++++
2 files changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7456bd2..d60a510 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5834,6 +5834,7 @@ enum skl_disp_power_wells {
# define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC ((1<<10) | (1<<26))
# define GEN9_RHWO_OPTIMIZATION_DISABLE (1<<14)
#define COMMON_SLICE_CHICKEN2 0x7014
+#define GEN9_DISABLE_GATHER_SET_SHADER_SLICE (1<<12)
# define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE (1<<0)
#define HIZ_CHICKEN 0x7018
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 5559ed9..e79be4c 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1305,6 +1305,15 @@ static int gen9_init_perctx_bb(struct intel_engine_cs *ring,
struct drm_device *dev = ring->dev;
uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);
+ /* WaNoName:skl,bxt
+ * This WA has no name, WA ID 0555 in spec says, driver needs to reset
+ * "disable gather at set shader slice" bit in per ctx batch
+ */
+ wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1));
+ wa_ctx_emit(batch, index, COMMON_SLICE_CHICKEN2);
+ wa_ctx_emit(batch, index,
+ _MASKED_BIT_DISABLE(GEN9_DISABLE_GATHER_SET_SHADER_SLICE));
+
/* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
if ((IS_SKYLAKE(dev) && (INTEL_REVID(dev) <= SKL_REVID_B0)) ||
(IS_BROXTON(dev) && (INTEL_REVID(dev) == BXT_REVID_A0))) {
--
1.9.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH v2] drm/i915:gen9: Add WA for disable gather at set shader bit
2015-08-12 16:03 ` Arun Siluvery
@ 2015-08-15 12:12 ` shuang.he
0 siblings, 0 replies; 7+ messages in thread
From: shuang.he @ 2015-08-15 12:12 UTC (permalink / raw)
To: shuang.he, julianx.dumez, christophe.sureau, lei.a.liu, intel-gfx,
arun.siluvery
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 7158
-------------------------------------Summary-------------------------------------
Platform Delta drm-intel-nightly Series Applied
ILK 302/302 302/302
SNB 315/315 315/315
IVB 336/336 336/336
BYT -1 283/283 282/283
HSW 378/378 378/378
-------------------------------------Detailed-------------------------------------
Platform Test drm-intel-nightly Series Applied
*BYT igt@gem_tiled_partial_pwrite_pread@reads PASS(1) FAIL(1)
Note: You need to pay more attention to line start with '*'
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v2] drm/i915:gen9: Add WA for disable gather at set shader bit
2015-08-12 13:34 ` [PATCH v2] " Arun Siluvery
@ 2015-08-15 12:13 ` shuang.he
0 siblings, 0 replies; 7+ messages in thread
From: shuang.he @ 2015-08-15 12:13 UTC (permalink / raw)
To: shuang.he, julianx.dumez, christophe.sureau, lei.a.liu, intel-gfx,
arun.siluvery
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 7158
-------------------------------------Summary-------------------------------------
Platform Delta drm-intel-nightly Series Applied
ILK 302/302 302/302
SNB 315/315 315/315
IVB 336/336 336/336
BYT -1 283/283 282/283
HSW 378/378 378/378
-------------------------------------Detailed-------------------------------------
Platform Test drm-intel-nightly Series Applied
*BYT igt@gem_tiled_partial_pwrite_pread@reads PASS(1) FAIL(1)
Note: You need to pay more attention to line start with '*'
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 7+ messages in thread
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Thread overview: 7+ messages (download: mbox.gz follow: Atom feed
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2015-08-07 17:33 [PATCH] drm/i915:gen9: Add WA for disable gather at set shader bit Arun Siluvery
2015-08-08 5:35 ` Ben Widawsky
2015-08-10 9:36 ` Siluvery, Arun
2015-08-12 13:34 ` [PATCH v2] " Arun Siluvery
2015-08-15 12:13 ` shuang.he
2015-08-12 16:03 ` Arun Siluvery
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