public inbox for intel-gfx@lists.freedesktop.org
 help / color / mirror / Atom feed
From: "Sharma, Shashank" <shashank.sharma@intel.com>
To: Vidya Srinivas <vidya.srinivas@intel.com>,
	intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 16/16] drm/i915: Enable YUV to RGB for Gen10 in Plane Ctrl Reg
Date: Thu, 15 Feb 2018 16:33:37 +0530	[thread overview]
Message-ID: <eb39ca75-b605-22ff-36f2-7f11fcaca7b2@intel.com> (raw)
In-Reply-To: <1518584256-25253-17-git-send-email-vidya.srinivas@intel.com>

My previous review comment for alignment has not been addressed in this 
series

Regards
Shashank
On 2/14/2018 10:27 AM, Vidya Srinivas wrote:
> If the fb format is YUV, enable the plane CSC mode bits
> for the conversion.
>
> Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
> ---
>   drivers/gpu/drm/i915/i915_reg.h      | 6 ++++++
>   drivers/gpu/drm/i915/intel_display.c | 2 ++
>   2 files changed, 8 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 10edacc..baf197b 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6453,6 +6453,12 @@ enum {
>   #define _PLANE_COLOR_CTL_3_A			0x703CC /* GLK+ */
>   #define   PLANE_COLOR_PIPE_GAMMA_ENABLE		(1 << 30)
>   #define   PLANE_COLOR_PIPE_CSC_ENABLE		(1 << 23)
> +#define PLANE_COLOR_CSC_MASK	(0x7 << 17)
> +#define PLANE_COLOR_CSC_MODE_BYPASS	(0 << 17)
> +#define PLANE_COLOR_CSC_MODE_YUV601_TO_RGB709	(1 << 17)
> +#define PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709	(2 << 17)
> +#define PLANE_COLOR_CSC_MODE_YUV2020_TO_RGB2020	(3 << 17)
> +#define PLANE_COLOR_CSC_MODE_RGB709_TO_RGB2020	(4 << 17)
>   #define   PLANE_COLOR_PLANE_GAMMA_DISABLE	(1 << 13)
>   #define   PLANE_COLOR_ALPHA_MASK		(0x3 << 4)
>   #define   PLANE_COLOR_ALPHA_DISABLE		(0 << 4)
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 42ec089..6c43eef 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3577,6 +3577,8 @@ u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
>   	plane_color_ctl |= PLANE_COLOR_PIPE_CSC_ENABLE;
>   	plane_color_ctl |= PLANE_COLOR_PLANE_GAMMA_DISABLE;
>   	plane_color_ctl |= glk_plane_color_ctl_alpha(fb->format->format);
> +	if (fb && intel_format_is_yuv(fb->format->format))
> +		plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709;
>   
>   	return plane_color_ctl;
>   }

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

  reply	other threads:[~2018-02-15 11:03 UTC|newest]

Thread overview: 52+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-02-14  4:57 [PATCH 00/16] Adding NV12 support Vidya Srinivas
2018-02-14  4:57 ` [PATCH 01/16] drm/i915/skl+: rename skl_wm_values struct to skl_ddb_values Vidya Srinivas
2018-02-14  4:57 ` [PATCH 02/16] drm/i915/skl+: refactor WM calculation for NV12 Vidya Srinivas
2018-02-14  4:57 ` [PATCH 03/16] drm/i915/skl+: add NV12 in skl_format_to_fourcc Vidya Srinivas
2018-02-14  4:57 ` [PATCH 04/16] drm/i915/skl+: support verification of DDB HW state for NV12 Vidya Srinivas
2018-02-14  9:36   ` Sharma, Shashank
2018-02-14  4:57 ` [PATCH 05/16] drm/i915/skl+: NV12 related changes for WM Vidya Srinivas
2018-02-14  9:41   ` Sharma, Shashank
2018-02-14  4:57 ` [PATCH 06/16] drm/i915/skl+: pass skl_wm_level struct to wm compute func Vidya Srinivas
2018-02-14  4:57 ` [PATCH 07/16] drm/i915/skl+: make sure higher latency level has higher wm value Vidya Srinivas
2018-02-14  4:57 ` [PATCH 08/16] drm/i915/skl+: nv12 workaround disable WM level 1-7 Vidya Srinivas
2018-02-14  9:47   ` Sharma, Shashank
2018-02-14  4:57 ` [PATCH 09/16] drm/i915/skl: split skl_compute_ddb function Vidya Srinivas
2018-02-14 10:02   ` Sharma, Shashank
2018-02-14  4:57 ` [PATCH 10/16] drm/i915: Set scaler mode for NV12 Vidya Srinivas
2018-02-15  6:32   ` Sharma, Shashank
2018-02-15  9:28     ` Srinivas, Vidya
2018-02-14  4:57 ` [PATCH 11/16] drm/i915: Update format_is_yuv() to include NV12 Vidya Srinivas
2018-02-15  6:34   ` Sharma, Shashank
2018-02-15  9:25     ` Srinivas, Vidya
2018-02-14  4:57 ` [PATCH 12/16] drm/i915: Upscale scaler max scale for NV12 Vidya Srinivas
2018-02-14  4:57 ` [PATCH 13/16] drm/i915: Add NV12 as supported format for primary plane Vidya Srinivas
2018-02-14  4:57 ` [PATCH 14/16] drm/i915: Add NV12 as supported format for sprite plane Vidya Srinivas
2018-02-15  8:53   ` Sharma, Shashank
2018-02-15  9:18     ` Srinivas, Vidya
2018-02-14  4:57 ` [PATCH 15/16] drm/i915: Add NV12 support to intel_framebuffer_init Vidya Srinivas
2018-02-15  9:22   ` Sharma, Shashank
2018-02-14  4:57 ` [PATCH 16/16] drm/i915: Enable YUV to RGB for Gen10 in Plane Ctrl Reg Vidya Srinivas
2018-02-15 11:03   ` Sharma, Shashank [this message]
2018-02-15 11:05   ` Sharma, Shashank
2018-02-14  5:24 ` [PATCH 00/16] Adding NV12 support Kristian Høgsberg
2018-02-14  8:32   ` Srinivas, Vidya
2018-02-14  5:46 ` ✗ Fi.CI.BAT: failure for Adding NV12 support (rev10) Patchwork
2018-02-14 12:33 ` ✗ Fi.CI.CHECKPATCH: warning " Patchwork
2018-02-14 12:37 ` ✗ Fi.CI.SPARSE: " Patchwork
2018-02-14 13:07   ` Maarten Lankhorst
2018-02-14 14:03     ` Arkadiusz Hiler
2018-02-14 12:48 ` ✓ Fi.CI.BAT: success " Patchwork
2018-02-14 14:10 ` ✗ Fi.CI.CHECKPATCH: warning " Patchwork
2018-02-14 14:14 ` ✗ Fi.CI.SPARSE: " Patchwork
2018-02-14 14:26 ` ✓ Fi.CI.BAT: success " Patchwork
2018-02-14 14:29 ` ✓ Fi.CI.IGT: " Patchwork
2018-02-14 14:48   ` Maarten Lankhorst
2018-02-14 18:53 ` ✗ Fi.CI.IGT: failure " Patchwork
2018-02-14 20:02 ` ✗ Fi.CI.IGT: warning " Patchwork
  -- strict thread matches above, loose matches on Subject: below --
2018-02-21 10:20 [PATCH 00/16] Adding NV12 support Vidya Srinivas
2018-02-21 10:20 ` [PATCH 16/16] drm/i915: Enable YUV to RGB for Gen10 in Plane Ctrl Reg Vidya Srinivas
2018-02-15  2:39 [PATCH 00/16] Adding NV12 support Vidya Srinivas
2018-02-15  2:39 ` [PATCH 16/16] drm/i915: Enable YUV to RGB for Gen10 in Plane Ctrl Reg Vidya Srinivas
2018-02-13  9:51 [PATCH 00/16] Adding NV12 support Vidya Srinivas
2018-02-13  9:52 ` [PATCH 16/16] drm/i915: Enable YUV to RGB for Gen10 in Plane Ctrl Reg Vidya Srinivas
2018-02-06 13:02 [PATCH 00/16] Adding NV12 support Vidya Srinivas
2018-02-06 13:02 ` [PATCH 16/16] drm/i915: Enable YUV to RGB for Gen10 in Plane Ctrl Reg Vidya Srinivas
2018-02-06 12:58 [PATCH 00/16] Adding NV12 support Vidya Srinivas
2018-02-06 12:58 ` [PATCH 16/16] drm/i915: Enable YUV to RGB for Gen10 in Plane Ctrl Reg Vidya Srinivas
2018-02-08 12:09   ` Sharma, Shashank
2018-01-22 12:03 [PATCH 00/16] Adding NV12 support Vidya Srinivas
2018-01-22 12:03 ` [PATCH 16/16] drm/i915: Enable YUV to RGB for Gen10 in Plane Ctrl Reg Vidya Srinivas

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=eb39ca75-b605-22ff-36f2-7f11fcaca7b2@intel.com \
    --to=shashank.sharma@intel.com \
    --cc=intel-gfx@lists.freedesktop.org \
    --cc=vidya.srinivas@intel.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox