Re: [PATCH 1/8] drm/i915: Convert intel_rc6_residency_us to ns

Chris Wilson
2017-09-25T17:08:56Z

Quoting Tvrtko Ursulin (2017-09-25 16:15:36)
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>
> Will be used for exposing the PMU counters.
>
> v2:
> * Move intel_runtime_pm_get/put to the callers. (Chris Wilson)
> * Restore full unit conversion precision.
>
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 8 +++++++-
> drivers/gpu/drm/i915/i915_sysfs.c | 9 +++++++--
> drivers/gpu/drm/i915/intel_pm.c | 27 +++++++++++++--------------
> 3 files changed, 27 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index c1e93a61d81b..ee03e839356f 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -4128,9 +4128,15 @@ void vlv_phy_reset_lanes(struct intel_encoder *encoder);
>
> int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
> int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
> -u64 intel_rc6_residency_us(struct drm_i915_private *dev_priv,
> +u64 intel_rc6_residency_ns(struct drm_i915_private *dev_priv,
> const i915_reg_t reg);
>
> +static inline u64 intel_rc6_residency_us(struct drm_i915_private *dev_priv,
> + const i915_reg_t reg)
> +{
> + return DIV_ROUND_UP_ULL(intel_rc6_residency_ns(dev_priv, reg), 1000);
> +}
> +
> #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
> #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
>
> diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
> index d61c8727f756..1a34d32d0092 100644
> --- a/drivers/gpu/drm/i915/i915_sysfs.c
> +++ b/drivers/gpu/drm/i915/i915_sysfs.c
> @@ -42,8 +42,13 @@ static inline struct drm_i915_private *kdev_minor_to_i915(struct device *kdev)
> static u32 calc_residency(struct drm_i915_private *dev_priv,
> i915_reg_t reg)
> {
> - return DIV_ROUND_CLOSEST_ULL(intel_rc6_residency_us(dev_priv, reg),
> - 1000);
> + u64 res;
> +
> + intel_runtime_pm_get(dev_priv);
> + res = intel_rc6_residency_us(dev_priv, reg);
> + intel_runtime_pm_put(dev_priv);
> +
> + return DIV_ROUND_CLOSEST_ULL(res, 1000);
> }
>
> static ssize_t
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index c66af09e27a7..8b4ffff11cf7 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -9343,34 +9343,33 @@ static u64 vlv_residency_raw(struct drm_i915_private *dev_priv,
> return lower | (u64)upper << 8;
> }
>
> -u64 intel_rc6_residency_us(struct drm_i915_private *dev_priv,
> +u64 intel_rc6_residency_ns(struct drm_i915_private *dev_priv,
> const i915_reg_t reg)
> {
> - u64 time_hw, units, div;
> + u64 time_hw;
> + u32 mul, div;

time_hw is a u32... except for vlv!

>
> if (!intel_enable_rc6())
> return 0;
>
> - intel_runtime_pm_get(dev_priv);
> -
> /* On VLV and CHV, residency time is in CZ units rather than 1.28us */
> if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
> - units = 1000;
> + mul = 1 000 000;
> div = dev_priv->czclk_freq;

Ok, scaling; previously returned us, now needs to be x1000 for ns.

> -
> time_hw = vlv_residency_raw(dev_priv, reg);
> - } else if (IS_GEN9_LP(dev_priv)) {
> - units = 1000;
> - div = 1200; /* 833.33ns */
>
> - time_hw = I915_READ(reg);
> } else {
> - units = 128000; /* 1.28us */
> - div = 100000;
> + /* 833.33ns units on Gen9LP, 1.28us elsewhere. */
> + if (IS_GEN9_LP(dev_priv)) {
> + mul = 10000;
> + div = 12;

Ok.

> + } else {
> + mul = 1280;
> + div = 1;

Ok.
> + }
>
> time_hw = I915_READ(reg);
> }
>
> - intel_runtime_pm_put(dev_priv);
> - return DIV_ROUND_UP_ULL(time_hw * units, div);
> + return DIV_ROUND_UP_ULL(time_hw * mul, div);
> }

Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris