Re: [PATCH 08/31] drm/i915: Rename intel_enable_rc6 to intel_rc6_enabled

Sagar Arun Kamble
2017-09-28T09:11:57Z

Thank you Radek, Ewelina for the reviews.

On 9/26/2017 1:11 PM, Ewelina Musial wrote:
> On Tue, Sep 19, 2017 at 11:11:44PM +0530, Sagar Arun Kamble wrote:
>> This function gives the status of RC6, whether disabled or if
>> enabled then which state. intel_enable_rc6 will be used for
>> enabling RC6 in the next patch.
>>
>> Cc: Chris Wilson <chris@chris-wilson.co.uk>
>> Cc: Imre Deak <imre.deak@intel.com>
>> Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
> Reviewed-by: Ewelina Musial <ewelina.musial@intel.com>
>
> - Ewelina
>> ---
>> drivers/gpu/drm/i915/i915_drv.c | 2 +-
>> drivers/gpu/drm/i915/i915_sysfs.c | 2 +-
>> drivers/gpu/drm/i915/intel_drv.h | 2 +-
>> drivers/gpu/drm/i915/intel_guc.c | 3 ++-
>> drivers/gpu/drm/i915/intel_pm.c | 12 ++++++------
>> 5 files changed, 11 insertions(+), 10 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
>> index 6cc1162..a6dbad3 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.c
>> +++ b/drivers/gpu/drm/i915/i915_drv.c
>> @@ -2486,7 +2486,7 @@ static int intel_runtime_suspend(struct device *kdev)
>> struct drm_i915_private *dev_priv = to_i915(dev);
>> int ret;
>>
>> - if (WARN_ON_ONCE(!(dev_priv->pm.rps.enabled && intel_enable_rc6())))
>> + if (WARN_ON_ONCE(!(dev_priv->pm.rps.enabled && intel_rc6_enabled())))
>> return -ENODEV;
>>
>> if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
>> diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
>> index c16e907..8add849 100644
>> --- a/drivers/gpu/drm/i915/i915_sysfs.c
>> +++ b/drivers/gpu/drm/i915/i915_sysfs.c
>> @@ -49,7 +49,7 @@ static u32 calc_residency(struct drm_i915_private *dev_priv,
>> static ssize_t
>> show_rc6_mask(struct device *kdev, struct device_attribute *attr, char *buf)
>> {
>> - return snprintf(buf, PAGE_SIZE, "%x\n", intel_enable_rc6());
>> + return snprintf(buf, PAGE_SIZE, "%x\n", intel_rc6_enabled());
>> }
>>
>> static ssize_t
>> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
>> index f7db720..0cf04eb 100644
>> --- a/drivers/gpu/drm/i915/intel_drv.h
>> +++ b/drivers/gpu/drm/i915/intel_drv.h
>> @@ -1900,7 +1900,7 @@ int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
>> struct intel_crtc_state *cstate);
>> void intel_init_ipc(struct drm_i915_private *dev_priv);
>> void intel_enable_ipc(struct drm_i915_private *dev_priv);
>> -static inline int intel_enable_rc6(void)
>> +static inline int intel_rc6_enabled(void)
>> {
>> return i915.enable_rc6;
>> }
>> diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
>> index c731cff..f4dc708 100644
>> --- a/drivers/gpu/drm/i915/intel_guc.c
>> +++ b/drivers/gpu/drm/i915/intel_guc.c
>> @@ -128,7 +128,8 @@ int intel_guc_sample_forcewake(struct intel_guc *guc)
>>
>> action[0] = INTEL_GUC_ACTION_SAMPLE_FORCEWAKE;
>> /* WaRsDisableCoarsePowerGating:skl,bxt */
>> - if (!intel_enable_rc6() || NEEDS_WaRsDisableCoarsePowerGating(dev_priv))
>> + if (!intel_rc6_enabled() ||
>> + NEEDS_WaRsDisableCoarsePowerGating(dev_priv))
>> action[1] = 0;
>> else
>> /* bit 0 and 1 are for Render and Media domain separately */
>> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
>> index b89677a..b83751e 100644
>> --- a/drivers/gpu/drm/i915/intel_pm.c
>> +++ b/drivers/gpu/drm/i915/intel_pm.c
>> @@ -6606,7 +6606,7 @@ static void gen9_enable_rc6(struct drm_i915_private *dev_priv)
>> I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);
>>
>> /* 3a: Enable RC6 */
>> - if (intel_enable_rc6() & INTEL_RC6_ENABLE)
>> + if (intel_rc6_enabled() & INTEL_RC6_ENABLE)
>> rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
>> DRM_INFO("RC6 %s\n", onoff(rc6_mask & GEN6_RC_CTL_RC6_ENABLE));
>> I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
>> @@ -6655,7 +6655,7 @@ static void gen8_enable_rc6(struct drm_i915_private *dev_priv)
>> I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
>>
>> /* 3: Enable RC6 */
>> - if (intel_enable_rc6() & INTEL_RC6_ENABLE)
>> + if (intel_rc6_enabled() & INTEL_RC6_ENABLE)
>> rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
>> intel_print_rc6_info(dev_priv, rc6_mask);
>> I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
>> @@ -6749,7 +6749,7 @@ static void gen6_enable_rc6(struct drm_i915_private *dev_priv)
>> I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
>>
>> /* Check if we are enabling RC6 */
>> - rc6_mode = intel_enable_rc6();
>> + rc6_mode = intel_rc6_enabled();
>> if (rc6_mode & INTEL_RC6_ENABLE)
>> rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
>>
>> @@ -7251,7 +7251,7 @@ static void cherryview_enable_rc6(struct drm_i915_private *dev_priv)
>> pcbr = I915_READ(VLV_PCBR);
>>
>> /* 3: Enable RC6 */
>> - if ((intel_enable_rc6() & INTEL_RC6_ENABLE) &&
>> + if ((intel_rc6_enabled() & INTEL_RC6_ENABLE) &&
>> (pcbr >> VLV_PCBR_ADDR_SHIFT))
>> rc6_mode = GEN7_RC_CTL_TO_MODE;
>>
>> @@ -7345,7 +7345,7 @@ static void valleyview_enable_rc6(struct drm_i915_private *dev_priv)
>> VLV_MEDIA_RC6_COUNT_EN |
>> VLV_RENDER_RC6_COUNT_EN));
>>
>> - if (intel_enable_rc6() & INTEL_RC6_ENABLE)
>> + if (intel_rc6_enabled() & INTEL_RC6_ENABLE)
>> rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
>>
>> intel_print_rc6_info(dev_priv, rc6_mode);
>> @@ -9418,7 +9418,7 @@ u64 intel_rc6_residency_us(struct drm_i915_private *dev_priv,
>> {
>> u64 time_hw, units, div;
>>
>> - if (!intel_enable_rc6())
>> + if (!intel_rc6_enabled())
>> return 0;
>>
>> intel_runtime_pm_get(dev_priv);
>> --
>> 1.9.1
>>
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