From: shuang.he@intel.com
To: shuang.he@intel.com, ethan.gao@intel.com,
intel-gfx@lists.freedesktop.org, sonika.jindal@intel.com
Subject: Re: [PATCH] drm/i915/skl: Enabling PSR2 SU with frame sync
Date: 26 Mar 2015 08:01:59 -0700 [thread overview]
Message-ID: <edcf24$e33e2t@FMSMGA003.fm.intel.com> (raw)
In-Reply-To: <1427358428-11370-1-git-send-email-sonika.jindal@intel.com>
Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 6057
-------------------------------------Summary-------------------------------------
Platform Delta drm-intel-nightly Series Applied
PNV -1 276/276 275/276
ILK 303/303 303/303
SNB 304/304 304/304
IVB 339/339 339/339
BYT 287/287 287/287
HSW 362/362 362/362
BDW 310/310 310/310
-------------------------------------Detailed-------------------------------------
Platform Test drm-intel-nightly Series Applied
PNV igt@gem_userptr_blits@minor-normal-sync DMESG_WARN(1)PASS(2) DMESG_WARN(1)PASS(1)(dmesg patch applied)WARNING:at_drivers/gpu/drm/i915/i915_gem_evict.c:#i915_gem_evict_vm[i915]()@WARNING:.* at .* i915_gem_evict_vm+0x
Note: You need to pay more attention to line start with '*'
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next prev parent reply other threads:[~2015-03-26 15:02 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-03-20 5:57 [PATCH] drm/i915/skl: Enabling PSR2 SU with frame sync Sonika Jindal
2015-03-20 9:09 ` shuang.he
2015-03-20 21:20 ` Vivi, Rodrigo
2015-03-23 4:38 ` sonika
2015-03-20 23:26 ` Vivi, Rodrigo
2015-03-23 8:48 ` sonika
2015-03-23 9:14 ` Daniel Vetter
2015-03-23 20:00 ` Vivi, Rodrigo
2015-03-26 8:27 ` Sonika Jindal
2015-03-26 11:39 ` R, Durgadoss
2015-03-30 11:34 ` Jindal, Sonika
2015-03-31 5:58 ` Sonika Jindal
2015-03-31 6:33 ` R, Durgadoss
2015-03-31 12:28 ` Daniel Vetter
2015-04-02 5:32 ` Sonika Jindal
2015-04-02 6:33 ` shuang.he
2015-04-07 8:07 ` Daniel Vetter
2015-03-31 12:40 ` shuang.he
2015-03-26 15:01 ` shuang.he [this message]
2015-03-23 8:40 ` Sivakumar Thulasimani
2015-03-24 4:33 ` sonika
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