[PATCH 0/5] drm/i915: gen2 fixes

[PATCH 0/5] drm/i915: gen2 fixes

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

I got annoyed at module reload not working properly on my 830, so I went
ahead and fixed. I also had to fix the overlay code a bit to not oops on
me on reload.

Also while writing the watermark register dumper, I noticed that we lacked
SR support for 85x, so I made a patch to enable it. I suspect g33 is
another platform which could have SR (since 945G and PNV both apparently
have it) but we don't enable it, but I don't have the hardware to verify
that.

Ville Syrjälä (5):
  drm/i915: Enable DVO 2x clock around DVO encoder init
  drm/i915: Convert BUGs to WARNs in the video overlay code
  drm/i915: Convert overlay->{active,pfit_active} to bools
  drm/i915: Mark the overlay active only if we got ring space
  drm/i915: Enable mmeory self-refresh on 85x

 drivers/gpu/drm/i915/i915_reg.h      |  1 +
 drivers/gpu/drm/i915/intel_dvo.c     | 17 +++++++++++++++++
 drivers/gpu/drm/i915/intel_overlay.c | 36 ++++++++++++++++++------------------
 drivers/gpu/drm/i915/intel_pm.c      |  4 ++++
 4 files changed, 40 insertions(+), 18 deletions(-)

-- 
2.0.5

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[PATCH 1/5] drm/i915: Enable DVO 2x clock around DVO encoder init

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

ns2501 requires the DVO 2x clock before it will respond to i2c access,
so make sure the clock is enabled when we try to initialize the encoder.

Fixes the display getting lost on module reload on my Fujitsu/Siemens
Lifebook S6010.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_dvo.c | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_dvo.c b/drivers/gpu/drm/i915/intel_dvo.c
index 4ccd6c3..f2ed122 100644
--- a/drivers/gpu/drm/i915/intel_dvo.c
+++ b/drivers/gpu/drm/i915/intel_dvo.c
@@ -495,6 +495,8 @@ void intel_dvo_init(struct drm_device *dev)
 		struct i2c_adapter *i2c;
 		int gpio;
 		bool dvoinit;
+		enum pipe pipe;
+		uint32_t dpll[2];
 
 		/* Allow the I2C driver info to specify the GPIO to be used in
 		 * special cases, but otherwise default to what's defined
@@ -520,8 +522,23 @@ void intel_dvo_init(struct drm_device *dev)
 		 */
 		intel_gmbus_force_bit(i2c, true);
 
+		/* ns2501 requires the DVO 2x clock before it will
+		 * respond to i2c accesses, so make sure we have
+		 * have the clock enabled before we attempt to
+		 * initialize the device.
+		 */
+		for_each_pipe(dev_priv, pipe) {
+			dpll[pipe] = I915_READ(DPLL(pipe));
+			I915_WRITE(DPLL(pipe), dpll[pipe] | DPLL_DVO_2X_MODE);
+		}
+
 		dvoinit = dvo->dev_ops->init(&intel_dvo->dev, i2c);
 
+		/* restore the DVO 2x clock state to original */
+		for_each_pipe(dev_priv, pipe) {
+			I915_WRITE(DPLL(pipe), dpll[pipe]);
+		}
+
 		intel_gmbus_force_bit(i2c, false);
 
 		if (!dvoinit)
-- 
2.0.5

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[PATCH 2/5] drm/i915: Convert BUGs to WARNs in the video overlay code

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

BUG is bad, just use WARN.

Also drop one BUG(!overlay) since we'd oops anyway when dereferencing
it.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_overlay.c | 22 +++++++++++-----------
 1 file changed, 11 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_overlay.c b/drivers/gpu/drm/i915/intel_overlay.c
index dd92122..730ee46 100644
--- a/drivers/gpu/drm/i915/intel_overlay.c
+++ b/drivers/gpu/drm/i915/intel_overlay.c
@@ -216,7 +216,7 @@ static int intel_overlay_do_wait_request(struct intel_overlay *overlay,
 	struct intel_engine_cs *ring = &dev_priv->ring[RCS];
 	int ret;
 
-	BUG_ON(overlay->last_flip_req);
+	WARN_ON(overlay->last_flip_req);
 	i915_gem_request_assign(&overlay->last_flip_req,
 					     ring->outstanding_lazy_request);
 	ret = i915_add_request(ring);
@@ -241,7 +241,7 @@ static int intel_overlay_on(struct intel_overlay *overlay)
 	struct intel_engine_cs *ring = &dev_priv->ring[RCS];
 	int ret;
 
-	BUG_ON(overlay->active);
+	WARN_ON(overlay->active);
 	overlay->active = 1;
 
 	WARN_ON(IS_I830(dev) && !(dev_priv->quirks & QUIRK_PIPEA_FORCE));
@@ -270,7 +270,7 @@ static int intel_overlay_continue(struct intel_overlay *overlay,
 	u32 tmp;
 	int ret;
 
-	BUG_ON(!overlay->active);
+	WARN_ON(!overlay->active);
 
 	if (load_polyphase_filter)
 		flip_addr |= OFC_UPDATE;
@@ -309,7 +309,8 @@ static void intel_overlay_off_tail(struct intel_overlay *overlay)
 	struct drm_i915_gem_object *obj = overlay->vid_bo;
 
 	/* never have the overlay hw on without showing a frame */
-	BUG_ON(!overlay->vid_bo);
+	if (WARN_ON(!obj))
+		return;
 
 	i915_gem_object_ggtt_unpin(obj);
 	drm_gem_object_unreference(&obj->base);
@@ -329,7 +330,7 @@ static int intel_overlay_off(struct intel_overlay *overlay)
 	u32 flip_addr = overlay->flip_addr;
 	int ret;
 
-	BUG_ON(!overlay->active);
+	WARN_ON(!overlay->active);
 
 	/* According to intel docs the overlay hw may hang (when switching
 	 * off) without loading the filter coeffs. It is however unclear whether
@@ -712,9 +713,8 @@ static int intel_overlay_do_put_image(struct intel_overlay *overlay,
 	u32 swidth, swidthsw, sheight, ostride;
 	enum pipe pipe = overlay->crtc->pipe;
 
-	BUG_ON(!mutex_is_locked(&dev->struct_mutex));
-	BUG_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
-	BUG_ON(!overlay);
+	WARN_ON(!mutex_is_locked(&dev->struct_mutex));
+	WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
 
 	ret = intel_overlay_release_old_vid(overlay);
 	if (ret != 0)
@@ -824,8 +824,8 @@ int intel_overlay_switch_off(struct intel_overlay *overlay)
 	struct drm_device *dev = overlay->dev;
 	int ret;
 
-	BUG_ON(!mutex_is_locked(&dev->struct_mutex));
-	BUG_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
+	WARN_ON(!mutex_is_locked(&dev->struct_mutex));
+	WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
 
 	ret = intel_overlay_recover_from_interrupt(overlay);
 	if (ret != 0)
@@ -1432,7 +1432,7 @@ void intel_cleanup_overlay(struct drm_device *dev)
 	/* The bo's should be free'd by the generic code already.
 	 * Furthermore modesetting teardown happens beforehand so the
 	 * hardware should be off already */
-	BUG_ON(dev_priv->overlay->active);
+	WARN_ON(dev_priv->overlay->active);
 
 	drm_gem_object_unreference_unlocked(&dev_priv->overlay->reg_bo->base);
 	kfree(dev_priv->overlay);
-- 
2.0.5

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Re: [PATCH 2/5] drm/i915: Convert BUGs to WARNs in the video overlay code

[Chris Wilson]

On Tue, Mar 31, 2015 at 10:37:22AM +0300, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> BUG is bad, just use WARN.
> 
> Also drop one BUG(!overlay) since we'd oops anyway when dereferencing
> it.

Bonus points for erroring out rather than continuing to nose dive into a
crash. At least that way userspace should stop trying as well.
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre
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Re: [PATCH 2/5] drm/i915: Convert BUGs to WARNs in the video overlay code

[Ville Syrjälä]

On Tue, Mar 31, 2015 at 01:27:04PM +0100, Chris Wilson wrote:
> On Tue, Mar 31, 2015 at 10:37:22AM +0300, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > BUG is bad, just use WARN.
> > 
> > Also drop one BUG(!overlay) since we'd oops anyway when dereferencing
> > it.
> 
> Bonus points for erroring out rather than continuing to nose dive into a
> crash. At least that way userspace should stop trying as well.

I have the feeling it shouldn't really blow up if we keep going in these
cases. I didn't do a very thorough analysis though.

I didn't want to start coding too defensively as there's practically no
limit on how far down that path we could go. So a line has to be drawn
somewhere.

-- 
Ville Syrjälä
Intel OTC
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[PATCH 3/5] drm/i915: Convert overlay->{active, pfit_active} to bools

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

overlay.{active,pfit_active} are just on/off flags, so make them bool.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_overlay.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_overlay.c b/drivers/gpu/drm/i915/intel_overlay.c
index 730ee46..fd9ded7 100644
--- a/drivers/gpu/drm/i915/intel_overlay.c
+++ b/drivers/gpu/drm/i915/intel_overlay.c
@@ -172,8 +172,8 @@ struct intel_overlay {
 	struct intel_crtc *crtc;
 	struct drm_i915_gem_object *vid_bo;
 	struct drm_i915_gem_object *old_vid_bo;
-	int active;
-	int pfit_active;
+	bool active;
+	bool pfit_active;
 	u32 pfit_vscale_ratio; /* shifted-point number, (1<<12) == 1.0 */
 	u32 color_key;
 	u32 brightness, contrast, saturation;
@@ -242,7 +242,7 @@ static int intel_overlay_on(struct intel_overlay *overlay)
 	int ret;
 
 	WARN_ON(overlay->active);
-	overlay->active = 1;
+	overlay->active = true;
 
 	WARN_ON(IS_I830(dev) && !(dev_priv->quirks & QUIRK_PIPEA_FORCE));
 
@@ -318,7 +318,7 @@ static void intel_overlay_off_tail(struct intel_overlay *overlay)
 
 	overlay->crtc->overlay = NULL;
 	overlay->crtc = NULL;
-	overlay->active = 0;
+	overlay->active = false;
 }
 
 /* overlay needs to be disabled in OCMD reg */
@@ -1131,10 +1131,10 @@ int intel_overlay_put_image(struct drm_device *dev, void *data,
 		/* line too wide, i.e. one-line-mode */
 		if (mode->hdisplay > 1024 &&
 		    intel_panel_fitter_pipe(dev) == crtc->pipe) {
-			overlay->pfit_active = 1;
+			overlay->pfit_active = true;
 			update_pfit_vscale_ratio(overlay);
 		} else
-			overlay->pfit_active = 0;
+			overlay->pfit_active = false;
 	}
 
 	ret = check_overlay_dst(overlay, put_image_rec);
-- 
2.0.5

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[PATCH 4/5] drm/i915: Mark the overlay active only if we got ring space

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

After the GPU has wedged we can't turn on the overlay anymore. Only mark
it as active if we succeed in allocating ring space. This prevents a
WARN (previous;y a BUG) during driver unload if we attempted to use the
overlay after the GPU had already wedged.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_overlay.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_overlay.c b/drivers/gpu/drm/i915/intel_overlay.c
index fd9ded7..b291f13 100644
--- a/drivers/gpu/drm/i915/intel_overlay.c
+++ b/drivers/gpu/drm/i915/intel_overlay.c
@@ -242,14 +242,14 @@ static int intel_overlay_on(struct intel_overlay *overlay)
 	int ret;
 
 	WARN_ON(overlay->active);
-	overlay->active = true;
-
 	WARN_ON(IS_I830(dev) && !(dev_priv->quirks & QUIRK_PIPEA_FORCE));
 
 	ret = intel_ring_begin(ring, 4);
 	if (ret)
 		return ret;
 
+	overlay->active = true;
+
 	intel_ring_emit(ring, MI_OVERLAY_FLIP | MI_OVERLAY_ON);
 	intel_ring_emit(ring, overlay->flip_addr | OFC_UPDATE);
 	intel_ring_emit(ring, MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
-- 
2.0.5

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[PATCH 5/5] drm/i915: Enable mmeory self-refresh on 85x

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

We currently lack the code to enable CxSR on 85x. The hardware seems to
have a few different SR modes, but let's ust use the most
straightforward one and hope this saves a bit of extra power.

I haven't observed any ill effects with this enabled on my 855.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 1 +
 drivers/gpu/drm/i915/intel_pm.c | 4 ++++
 2 files changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b522eb6..45308c7 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1498,6 +1498,7 @@ enum skl_disp_power_wells {
 #define   MI_ARB_DISPLAY_PRIORITY_B_A		(1 << 0)	/* display B > display A */
 
 #define MI_STATE	0x020e4 /* gen2 only */
+#define   MI_SR_EN				(3 << 3) /* 85x only */
 #define   MI_AGPBUSY_INT_EN			(1 << 1) /* 85x only */
 #define   MI_AGPBUSY_830_MODE			(1 << 0) /* 85x only */
 
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index fa4ccb3..d23fb82 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -327,6 +327,10 @@ void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
 		val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
 			       _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
 		I915_WRITE(INSTPM, val);
+	} else if (IS_I85X(dev)) {
+		val = enable ? _MASKED_BIT_ENABLE(MI_SR_EN) :
+			       _MASKED_BIT_DISABLE(MI_SR_EN);
+		I915_WRITE(MI_STATE, val);
 	} else {
 		return;
 	}
-- 
2.0.5

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Re: [PATCH 5/5] drm/i915: Enable mmeory self-refresh on 85x

[shuang.he]

Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 6096
-------------------------------------Summary-------------------------------------
Platform          Delta          drm-intel-nightly          Series Applied
PNV                                  276/276              276/276
ILK                                  303/303              303/303
SNB                                  304/304              304/304
IVB                                  338/338              338/338
BYT                                  287/287              287/287
HSW                                  361/361              361/361
BDW                                  309/309              309/309
-------------------------------------Detailed-------------------------------------
Platform  Test                                drm-intel-nightly          Series Applied
Note: You need to pay more attention to line start with '*'
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