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d="scan'208";a="217201818" Received: from slindbla-desk.ger.corp.intel.com (HELO localhost) ([10.245.246.57]) by orviesa005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Feb 2026 04:46:21 -0800 From: Jani Nikula To: Uma Shankar , intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: ville.syrjala@linux.intel.com, Uma Shankar Subject: Re: [v4 08/20] drm/i915: Remove i915_reg.h from intel_dram.c In-Reply-To: <20260205094341.1882816-9-uma.shankar@intel.com> Organization: Intel Finland Oy - BIC 0357606-4 - c/o Alberga Business Park, 6 krs Bertel Jungin Aukio 5, 02600 Espoo, Finland References: <20260205094341.1882816-1-uma.shankar@intel.com> <20260205094341.1882816-9-uma.shankar@intel.com> Date: Wed, 11 Feb 2026 14:46:17 +0200 Message-ID: MIME-Version: 1.0 Content-Type: text/plain X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Thu, 05 Feb 2026, Uma Shankar wrote: > Make intel_dram.c free from including i915_reg.h. > > v3: Move MEM_SS info reg to display instead of pcode header (Jani) > > v2: Move mem config register to newly added pcode header (Jani) > > Signed-off-by: Uma Shankar Reviewed-by: Jani Nikula > --- > drivers/gpu/drm/i915/display/intel_display_regs.h | 6 ++++++ > drivers/gpu/drm/i915/display/intel_dram.c | 2 +- > drivers/gpu/drm/i915/i915_reg.h | 6 ------ > 3 files changed, 7 insertions(+), 7 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h > index c598ccb3c78b..42aef6300320 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_regs.h > +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h > @@ -3075,6 +3075,12 @@ enum skl_power_gate { > #define MTL_PIPE_CLKGATE_DIS2(pipe) _MMIO_PIPE(pipe, _MTL_PIPE_CLKGATE_DIS2_A, _MTL_PIPE_CLKGATE_DIS2_B) > #define MTL_DPFC_GATING_DIS REG_BIT(6) > > +#define MTL_MEM_SS_INFO_GLOBAL _MMIO(0x45700) > +#define XE3P_ECC_IMPACTING_DE REG_BIT(12) > +#define MTL_N_OF_ENABLED_QGV_POINTS_MASK REG_GENMASK(11, 8) > +#define MTL_N_OF_POPULATED_CH_MASK REG_GENMASK(7, 4) > +#define MTL_DDR_TYPE_MASK REG_GENMASK(3, 0) > + > #define MTL_MEM_SS_INFO_QGV_POINT_OFFSET 0x45710 > #define MTL_MEM_SS_INFO_QGV_POINT_LOW(point) _MMIO(MTL_MEM_SS_INFO_QGV_POINT_OFFSET + (point) * 8) > #define MTL_TRCD_MASK REG_GENMASK(31, 24) > diff --git a/drivers/gpu/drm/i915/display/intel_dram.c b/drivers/gpu/drm/i915/display/intel_dram.c > index 61aefe77f90f..bd281d4b4c05 100644 > --- a/drivers/gpu/drm/i915/display/intel_dram.c > +++ b/drivers/gpu/drm/i915/display/intel_dram.c > @@ -9,9 +9,9 @@ > #include > #include > > -#include "i915_reg.h" > #include "intel_display_core.h" > #include "intel_display_utils.h" > +#include "intel_display_regs.h" > #include "intel_dram.h" > #include "intel_mchbar_regs.h" > #include "intel_parent.h" > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index b12c6bf68a2c..e905250f4fa5 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -1005,12 +1005,6 @@ > #define OROM_OFFSET _MMIO(0x1020c0) > #define OROM_OFFSET_MASK REG_GENMASK(20, 16) > > -#define MTL_MEM_SS_INFO_GLOBAL _MMIO(0x45700) > -#define XE3P_ECC_IMPACTING_DE REG_BIT(12) > -#define MTL_N_OF_ENABLED_QGV_POINTS_MASK REG_GENMASK(11, 8) > -#define MTL_N_OF_POPULATED_CH_MASK REG_GENMASK(7, 4) > -#define MTL_DDR_TYPE_MASK REG_GENMASK(3, 0) > - > #define MTL_MEDIA_GSI_BASE 0x380000 > > #endif /* _I915_REG_H_ */ -- Jani Nikula, Intel