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Mon, 26 Sep 2022 16:28:14 +0000 Received: from DM4PR11MB5488.namprd11.prod.outlook.com ([fe80::280f:75b5:17ad:1668]) by DM4PR11MB5488.namprd11.prod.outlook.com ([fe80::280f:75b5:17ad:1668%3]) with mapi id 15.20.5654.026; Mon, 26 Sep 2022 16:28:14 +0000 Message-ID: Date: Mon, 26 Sep 2022 09:28:11 -0700 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.13.1 Content-Language: en-US To: Tvrtko Ursulin , References: <20220922221117.458087-1-daniele.ceraolospurio@intel.com> <20220922221117.458087-2-daniele.ceraolospurio@intel.com> <37c12259-2190-5299-8d4e-f9ec9fe8a2f5@linux.intel.com> From: "Ceraolo Spurio, Daniele" In-Reply-To: <37c12259-2190-5299-8d4e-f9ec9fe8a2f5@linux.intel.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-ClientProxiedBy: BYAPR07CA0060.namprd07.prod.outlook.com (2603:10b6:a03:60::37) To DM4PR11MB5488.namprd11.prod.outlook.com (2603:10b6:5:39d::5) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM4PR11MB5488:EE_|CH0PR11MB5362:EE_ X-MS-Office365-Filtering-Correlation-Id: 933518da-b0f2-4d83-4c4c-08da9fdc1c41 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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We must therefore skip the HuC fetch and load on >>>> that specific case. Given that other multi-GT platforms might have HuC >>>> on the primary GT, we can't just check for that and it is easier to >>>> instead check for the lack of VCS engines. >>>> >>>> Based on code from Aravind Iddamsetty >>>> >>>> Signed-off-by: Daniele Ceraolo Spurio >>>> >>>> Cc: Aravind Iddamsetty >>>> Cc: John Harrison >>>> Cc: Alan Previn >>>> --- >>>>   drivers/gpu/drm/i915/gt/uc/intel_huc.c | 21 +++++++++++++++++++++ >>>>   drivers/gpu/drm/i915/i915_drv.h        |  9 ++++++--- >>>>   2 files changed, 27 insertions(+), 3 deletions(-) >>>> >>>> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.c >>>> b/drivers/gpu/drm/i915/gt/uc/intel_huc.c >>>> index 3bb8838e325a..d4e2b252f16c 100644 >>>> --- a/drivers/gpu/drm/i915/gt/uc/intel_huc.c >>>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.c >>>> @@ -42,12 +42,33 @@ >>>>    * HuC-specific commands. >>>>    */ >>>>   +static bool vcs_supported(struct intel_gt *gt) >>>> +{ >>>> +    intel_engine_mask_t mask = gt->info.engine_mask; >>>> + >>>> +    /* >>>> +     * we can reach here from i915_driver_early_probe for primary >>>> +     * GT with it being not fully setup hence fall back to the >>>> device info's >>>> +     * engine mask >>>> +     */ >>>> +    if (!mask && gt_is_root(gt)) >>>> +        mask = RUNTIME_INFO(gt->i915)->platform_engine_mask; >>> >>> Is it possible for all instances to be fused off? Wondering if the >>> function shouldn't just use platform_engine_mask. >> >> The spec says that there is always going to be at least 1 VCS (bspec >> 55417 in case you want to double-check). I don't see that changing in >> the future, because what's the point of having a media GT if you >> don't have any enabled VCS engines on it? > > That was my gut feeling as well, however.. > >> Also, platform_engine_mask only contains the entries of the primary >> GT, for the other GTs we'd have to navigate the array in the device >> info structure and I don't think we want to do that from here when >> we've already copied the mask inside gt->info.engine_mask. > > ... this is very annoying. Because function is now a bit dodgy, no? > Maybe gets the caller a real answer for a _specific_ gt, or maybe gets > a fake-ish answer for a root gt. Or if not a root gt and called too > early maybe it returns a false zero? > > Hm would GEM_BUG_ON(!mask && !gt_is_root(gt)) be correct? > > And not even bother to implement is as fallback? > > if (gt_is_root) >     return platform_mask; > else >     return gt_mask; > > Would that be clearer? Coupled with the comment from the patch, maybe > expanded with the statement that if there are some vcs engines, at > least one must remain post fusing? This works for me. I'll wait a bit to see if there are comments on the other patches and then send an update. Thanks, Daniele > > Regards, > > Tvrtko > >>>> + >>>> +    return __ENGINE_INSTANCES_MASK(mask, VCS0, I915_MAX_VCS); >>>> +} >>>> + >>>>   void intel_huc_init_early(struct intel_huc *huc) >>>>   { >>>>       struct drm_i915_private *i915 = huc_to_gt(huc)->i915; >>>> +    struct intel_gt *gt = huc_to_gt(huc); >>>>         intel_uc_fw_init_early(&huc->fw, INTEL_UC_FW_TYPE_HUC); >>>>   +    if (!vcs_supported(gt)) { >>>> +        intel_uc_fw_change_status(&huc->fw, >>>> INTEL_UC_FIRMWARE_NOT_SUPPORTED); >>>> +        return; >>>> +    } >>>> + >>>>       if (GRAPHICS_VER(i915) >= 11) { >>>>           huc->status.reg = GEN11_HUC_KERNEL_LOAD_INFO; >>>>           huc->status.mask = HUC_LOAD_SUCCESSFUL; >>>> diff --git a/drivers/gpu/drm/i915/i915_drv.h >>>> b/drivers/gpu/drm/i915/i915_drv.h >>>> index 134fc1621821..8ca575202e5d 100644 >>>> --- a/drivers/gpu/drm/i915/i915_drv.h >>>> +++ b/drivers/gpu/drm/i915/i915_drv.h >>>> @@ -777,12 +777,15 @@ IS_SUBPLATFORM(const struct drm_i915_private >>>> *i915, >>>>   #define __HAS_ENGINE(engine_mask, id) ((engine_mask) & BIT(id)) >>>>   #define HAS_ENGINE(gt, id) __HAS_ENGINE((gt)->info.engine_mask, id) >>>>   -#define ENGINE_INSTANCES_MASK(gt, first, count) ({ \ >>>> +#define __ENGINE_INSTANCES_MASK(mask, first, count) ({            \ >>>>       unsigned int first__ = (first);                    \ >>>>       unsigned int count__ = (count);                    \ >>>> -    ((gt)->info.engine_mask & \ >>>> -     GENMASK(first__ + count__ - 1, first__)) >> first__;        \ >>>> +    ((mask) & GENMASK(first__ + count__ - 1, first__)) >> >>>> first__;    \ >>>>   }) >>>> + >>>> +#define ENGINE_INSTANCES_MASK(gt, first, count) \ >>>> +    __ENGINE_INSTANCES_MASK((gt)->info.engine_mask, first, count) >>>> + >>>>   #define RCS_MASK(gt) \ >>>>       ENGINE_INSTANCES_MASK(gt, RCS0, I915_MAX_RCS) >>>>   #define BCS_MASK(gt) \ >>