intel-gfx.lists.freedesktop.org archive mirror
 help / color / mirror / Atom feed
From: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
To: "Vivi, Rodrigo" <rodrigo.vivi@intel.com>
Cc: "intel-gfx@lists.freedesktop.org" <intel-gfx@lists.freedesktop.org>
Subject: Re: [PATCH 23/67] drm/i915/gen10: Set value of Indirect Context Offset for gen10
Date: Tue, 6 Jun 2017 07:48:03 +0100	[thread overview]
Message-ID: <f404cef3-df67-d35d-a041-bcdfc44d5307@linux.intel.com> (raw)
In-Reply-To: <1496682686.20038.14.camel@rdvivi-vienna>


On 05/06/2017 18:11, Vivi, Rodrigo wrote:
> On Fri, 2017-06-02 at 10:50 +0100, Tvrtko Ursulin wrote:
>> On 06/04/2017 20:15, Rodrigo Vivi wrote:
>>> From: Michel Thierry <michel.thierry@intel.com>
>>>
>>
>> Some commit message needed just to satisfy the form.
> 
> What about:
> 
> Indirect Context Offset Pointer has changed for Cannonlake.
> 
> INDIRECT_CTX_OFFSET[15:6] valid value for CNL is 19h per Spec.

Completely fine.

>>
>>> v2: rebased to intel_lr_indirect_ctx_offset
>>>
>>> Signed-off-by: Michel Thierry <michel.thierry@intel.com>
>>> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>>> ---
>>>    drivers/gpu/drm/i915/intel_lrc.c | 5 +++++
>>>    1 file changed, 5 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
>>> index f2d57b4..ac38469 100644
>>> --- a/drivers/gpu/drm/i915/intel_lrc.c
>>> +++ b/drivers/gpu/drm/i915/intel_lrc.c
>>> @@ -209,6 +209,7 @@
>>>    
>>>    #define GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT	0x17
>>>    #define GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT	0x26
>>> +#define GEN10_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT	0x19
>>>    
>>>    /* Typical size of the average request (2 pipecontrols and a MI_BB) */
>>>    #define EXECLISTS_REQUEST_SIZE 64 /* bytes */
>>> @@ -1787,6 +1788,10 @@ static u32 intel_lr_indirect_ctx_offset(struct intel_engine_cs *engine)
>>>    	default:
>>>    		MISSING_CASE(INTEL_GEN(engine->i915));
>>>    		/* fall through */
>>> +	case 10:
>>> +		indirect_ctx_offset =
>>> +			GEN10_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
>>> +		break;
>>>    	case 9:
>>>    		indirect_ctx_offset =
>>>    			GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
>>>
>>
>> After some documentation and commit log traversing to find the relevant
>> page, and with a short sentence in the commit message:
> 
> is the above enough?
> 
> Bspec index/11740
> or CNL:BUG:1929753

If we have decided to start putting in those that's fine by me.

Regards,

Tvrtko

> 
>>
>> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>
>> Regards,
>>
>> Tvrtko
> 
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

  reply	other threads:[~2017-06-06  6:48 UTC|newest]

Thread overview: 182+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-04-06 19:14 [PATCH 01/67] drm/i915/cnp: Introduce Cannonpoint PCH Rodrigo Vivi
2017-04-06 19:14 ` [PATCH 02/67] drm/i915/cnp: Add PCI ID for Cannonpoint LP PCH Rodrigo Vivi
2017-04-12 17:41   ` Srivatsa, Anusha
2017-04-06 19:14 ` [PATCH 03/67] drm/i915/cnp: Get/set proper Raw clock frequency on CNP Rodrigo Vivi
2017-04-07 13:45   ` Ville Syrjälä
2017-04-06 19:15 ` [PATCH 04/67] drm/i915/cnp: Add Backlight support to CNP PCH Rodrigo Vivi
2017-04-07 14:16   ` Ville Syrjälä
2017-04-11  8:33     ` Jani Nikula
2017-04-06 19:15 ` [PATCH 05/67] drm/i915/cnp: add CNP gmbus support Rodrigo Vivi
2017-04-07  0:54   ` [PATCH] " Rodrigo Vivi
2017-04-07 18:46     ` kbuild test robot
2017-04-17 21:13   ` [PATCH 05/67] " Srivatsa, Anusha
2017-04-06 19:15 ` [PATCH 06/67] drm/i915/cnp: Panel Power sequence changes for CNP PCH Rodrigo Vivi
2017-04-07 14:48   ` Ville Syrjälä
2017-04-13 23:48     ` Vivi, Rodrigo
2017-05-23 22:16       ` Ville Syrjälä
2017-04-06 19:15 ` [PATCH 07/67] drm/i915/cnl: Introduce Cannonlake platform defition Rodrigo Vivi
2017-05-04  8:55   ` Ander Conselvan De Oliveira
2017-04-06 19:15 ` [PATCH 08/67] drm/i915/cnl: Cannonlake uses CNP PCH Rodrigo Vivi
2017-05-03 23:46   ` Srivatsa, Anusha
2017-04-06 19:15 ` [PATCH 09/67] drm/i915/cnl: Add Cannonlake PCI IDs for U-skus Rodrigo Vivi
2017-06-02 16:07   ` Clint Taylor
2017-04-06 19:15 ` [PATCH 10/67] drm/i915/cnl: Add Cannonlake PCI IDs for Y-skus Rodrigo Vivi
2017-04-06 19:15 ` [PATCH 11/67] drm/i915/cnl: add IS_CNL_REVID macro Rodrigo Vivi
2017-05-11 15:37   ` Jim Bride
2017-04-06 19:15 ` [PATCH 12/67] drm/i915/cnl: Introduce initial Cannonlake Workarounds Rodrigo Vivi
2017-04-28 17:11   ` Oscar Mateo
2017-05-10 11:17   ` Ander Conselvan De Oliveira
2017-06-06 20:53     ` [PATCH] " Rodrigo Vivi
2017-06-07 20:47       ` kbuild test robot
2017-06-07 21:09       ` kbuild test robot
2017-04-06 19:15 ` [PATCH 13/67] drm/i915/cnl: Add WaDisableReplayBufferBankArbitrationOptimization Rodrigo Vivi
2017-06-08 16:54   ` Mika Kuoppala
2017-06-08 17:09     ` Vivi, Rodrigo
2017-04-06 19:15 ` [PATCH 14/67] drm/i915/cnl: WaDisableEnhancedSBEVertexCaching Rodrigo Vivi
2017-06-08 17:07   ` Mika Kuoppala
2017-04-06 19:15 ` [PATCH 15/67] drm/i915/cnl: Apply large line width optimization Rodrigo Vivi
2017-04-06 19:15 ` [PATCH 16/67] drm/i915/cnl: Cannonlake has 4 planes (3 sprites) per pipe Rodrigo Vivi
2017-05-04  9:10   ` Ander Conselvan De Oliveira
2017-04-06 19:15 ` [PATCH 17/67] drm/i915/cnl: CNL has an increased DDB size Rodrigo Vivi
2017-04-06 19:15 ` [PATCH 18/67] drm/i915/cnl: Add initial gen10 golden states Rodrigo Vivi
2017-04-06 19:15 ` [PATCH 19/67] drm/i915/cnl: Configure EU slice power gating Rodrigo Vivi
2017-06-02 11:27   ` Joonas Lahtinen
2017-04-06 19:15 ` [PATCH 20/67] drm/i915/cnl: Cannonlake has same MOCS table than Skylake Rodrigo Vivi
2017-06-02 11:20   ` Joonas Lahtinen
2017-04-06 19:15 ` [PATCH 21/67] drm/i915/cnl: Update the context size Rodrigo Vivi
2017-04-06 19:46   ` Chris Wilson
2017-04-06 21:53   ` Daniele Ceraolo Spurio
2017-04-06 21:56     ` Ben Widawsky
2017-04-06 19:15 ` [PATCH 22/67] drm/i915/cnl: Add RT cache flush pipe control w/a Rodrigo Vivi
2017-06-02 10:01   ` Tvrtko Ursulin
2017-06-05 17:17     ` Vivi, Rodrigo
2017-04-06 19:15 ` [PATCH 23/67] drm/i915/gen10: Set value of Indirect Context Offset for gen10 Rodrigo Vivi
2017-06-02  9:50   ` Tvrtko Ursulin
2017-06-05 17:11     ` Vivi, Rodrigo
2017-06-06  6:48       ` Tvrtko Ursulin [this message]
2017-06-06 15:18         ` Vivi, Rodrigo
2017-04-06 19:15 ` [PATCH 24/67] drm/i915/cnl: Add force wake " Rodrigo Vivi
2017-06-08 14:58   ` Joonas Lahtinen
2017-04-06 19:15 ` [PATCH 25/67] drm/i915/cnl: Inherit RPS stuff from previous platforms Rodrigo Vivi
2017-04-06 19:15 ` [PATCH 26/67] drm/i915/cnl: Add power wells for CNL Rodrigo Vivi
2017-06-05 15:55   ` Imre Deak
2017-06-05 16:42     ` Vivi, Rodrigo
2017-04-06 19:15 ` [PATCH 27/67] drm/i915/cnl: Also need power well sanitize Rodrigo Vivi
2017-04-13 14:44   ` Imre Deak
2017-04-13 16:03     ` Vivi, Rodrigo
2017-06-05 15:56   ` Imre Deak
2017-04-06 19:15 ` [PATCH 28/67] drm/i915/cnl: Implement .get_display_clock_speed() for CNL Rodrigo Vivi
2017-06-02 18:06   ` Imre Deak
2017-06-05 17:59     ` Vivi, Rodrigo
2017-06-05 18:04       ` Ville Syrjälä
2017-06-05 18:21         ` Imre Deak
2017-06-05 18:28           ` Vivi, Rodrigo
2017-06-05 20:07             ` Imre Deak
2017-06-06 21:56               ` Rodrigo Vivi
2017-06-07 10:59                 ` Ville Syrjälä
2017-06-07 11:09                   ` Ville Syrjälä
2017-06-07 14:22                     ` Rodrigo Vivi
2017-04-06 19:15 ` [PATCH 29/67] drm/i915/cnl: Implement .set_cdclk() " Rodrigo Vivi
2017-06-05 13:11   ` Imre Deak
2017-04-06 19:15 ` [PATCH 30/67] drm/i915/cnl: Implement CNL display init/unit sequence Rodrigo Vivi
2017-04-13 16:13   ` [PATCH] " Rodrigo Vivi
2017-06-05 15:07     ` Imre Deak
2017-06-05 16:38       ` Vivi, Rodrigo
2017-06-05 16:58         ` Imre Deak
2017-04-06 19:15 ` [PATCH 31/67] drm/i915/cnl: Allow dynamic cdclk changes on CNL Rodrigo Vivi
2017-06-05 15:22   ` Imre Deak
2017-06-05 16:41     ` Vivi, Rodrigo
2017-06-05 16:55       ` Ville Syrjälä
2017-06-05 17:04         ` Pandiyan, Dhinakaran
2017-06-06 15:24           ` Rodrigo Vivi
2017-06-06 17:39             ` Pandiyan, Dhinakaran
2017-06-06 18:09               ` Rodrigo Vivi
2017-06-06 18:12                 ` Rodrigo Vivi
2017-06-06 21:48                   ` Pandiyan, Dhinakaran
2017-06-06 21:57                     ` Rodrigo Vivi
2017-04-06 19:15 ` [PATCH 32/67] drm/i915/cnl: DDI - PLL mapping Rodrigo Vivi
2017-04-07 21:12   ` Paulo Zanoni
2017-05-04 12:35     ` Ander Conselvan De Oliveira
2017-05-04 12:44       ` Ville Syrjälä
2017-05-04 13:02         ` Maarten Lankhorst
2017-05-04 13:11           ` Ville Syrjälä
2017-05-23 19:42             ` Vivi, Rodrigo
2017-05-04 12:55   ` Ander Conselvan De Oliveira
2017-04-06 19:15 ` [PATCH 33/67] drm/i915: Configure DPLL's for Cannonlake Rodrigo Vivi
2017-05-04 13:16   ` Ander Conselvan De Oliveira
2017-04-06 19:15 ` [PATCH 34/67] drm/i915/cnl: Initialize PLLs Rodrigo Vivi
2017-04-06 19:15 ` [PATCH 35/67] drm/i915/cnl: Enable wrpll computation for CNL Rodrigo Vivi
2017-06-08 23:03   ` [PATCH] " Rodrigo Vivi
2017-06-08 23:24     ` Clint Taylor
2017-04-06 19:15 ` [PATCH 36/67] drm/i915: Add MMIO helper for 6 ports with different offsets Rodrigo Vivi
2017-05-17 19:20   ` Manasi Navare
2017-05-23 19:16     ` Rodrigo Vivi
2017-06-05 18:45     ` Manasi Navare
2017-04-06 19:15 ` [PATCH 37/67] drm/i915/cnl: Add registers related to voltage swing sequences Rodrigo Vivi
2017-05-18  0:59   ` Manasi Navare
2017-05-23 19:18     ` Vivi, Rodrigo
2017-06-05 18:47     ` Manasi Navare
2017-06-05 20:45       ` [PATCH] " Rodrigo Vivi
2017-06-05 20:46       ` Rodrigo Vivi
2017-06-06  0:03         ` Manasi Navare
2017-06-05 20:51       ` [PATCH] drm/i915/cnl: Implement voltage swing sequence Rodrigo Vivi
2017-06-05 20:53       ` Rodrigo Vivi
2017-06-06  0:00         ` Manasi Navare
2017-04-06 19:15 ` [PATCH 38/67] drm/i915/cnl: Add DDI Buffer translation tables for Cannonlake Rodrigo Vivi
2017-05-18  1:01   ` Manasi Navare
2017-04-06 19:15 ` [PATCH 39/67] drm/i915/cnl: Implement voltage swing sequence Rodrigo Vivi
2017-05-18  1:13   ` Manasi Navare
2017-05-23 19:19     ` Vivi, Rodrigo
2017-04-06 19:15 ` [PATCH 40/67] drm/i915/cnl: Enable loadgen_select bit for vswing sequence Rodrigo Vivi
2017-04-24 18:53   ` Ville Syrjälä
2017-05-18  1:17   ` Manasi Navare
2017-04-06 19:15 ` [PATCH 41/67] drm/i915/cnl: Add slice and subslice information to debugfs Rodrigo Vivi
2017-04-06 19:15 ` [PATCH 42/67] drm/i915/DMC/CNL: Load DMC on CNL Rodrigo Vivi
2017-05-22 10:43   ` Animesh Manna
2017-04-06 19:15 ` [PATCH 43/67] drm/i915: Use HAS_CSR instead of gen number on DMC load Rodrigo Vivi
2017-05-22 10:46   ` Animesh Manna
2017-04-06 19:15 ` [PATCH 44/67] drm/i915/cnl: DC3 to DC5 counters available on CNL Rodrigo Vivi
2017-05-22 12:55   ` Animesh Manna
2017-04-06 19:15 ` [PATCH 45/67] drm/i915/cnl: Add max allowed Cannonlake DC Rodrigo Vivi
2017-04-06 19:15 ` [PATCH 46/67] drm/i915/cnl: Add allowed DP rates for Cannonlake Rodrigo Vivi
2017-04-06 19:15 ` [PATCH 47/67] drm/i915/cnl: Dump the right pll registers when dumping pipe config Rodrigo Vivi
2017-04-06 19:15 ` [PATCH 48/67] drm/i915/cnl: Get DDI clock based on PLLs Rodrigo Vivi
2017-04-06 19:15 ` [PATCH 49/67] drm/i915/cnl: Avoid old DDI translation functions on Cannonlake Rodrigo Vivi
2017-04-06 19:15 ` [PATCH 50/67] drm/i915/gen10+: use the SKL code for reading WM latencies Rodrigo Vivi
2017-04-24 18:22   ` Ville Syrjälä
2017-04-24 19:10     ` Paulo Zanoni
2017-04-24 20:04       ` Ville Syrjälä
2017-04-06 19:15 ` [PATCH 51/67] drm/i915/cnl: Enable SAGV for Cannonlake Rodrigo Vivi
2017-04-06 19:15 ` [PATCH 52/67] drm/i915/gen10: fix the gen 10 SAGV block time Rodrigo Vivi
2017-04-06 19:15 ` [PATCH 53/67] drm/i915/cnl: don't apply the GEN9/CNL:A WM WAs to CNL:B+ Rodrigo Vivi
2017-05-24  8:40   ` Mahesh Kumar
2017-04-06 19:15 ` [PATCH 54/67] drm/i915/gen10: fix WM latency printing Rodrigo Vivi
2017-04-06 19:15 ` [PATCH 55/67] drm/i915/gen10: implement gen 10 watermarks calculations Rodrigo Vivi
2017-05-29  8:25   ` Ander Conselvan De Oliveira
2017-04-06 19:15 ` [PATCH 56/67] drm/i915/cnl: Reuse skl_wm_get_hw_state on Cannonlake Rodrigo Vivi
2017-04-06 19:15 ` [PATCH 57/67] x86/gpu: CNL uses the same GMS values as SKL Rodrigo Vivi
2017-04-06 19:39   ` [PATCH] " Rodrigo Vivi
2017-04-07 19:21     ` kbuild test robot
2017-04-07 19:21       ` Paulo Zanoni
2017-04-13  1:33         ` [kbuild-all] " Ye Xiaolong
2017-04-07 22:07     ` Thomas Gleixner
2017-04-06 19:15 ` [PATCH 58/67] drm/i915/cnl: Cannonlake color init Rodrigo Vivi
2017-04-24 17:57   ` Ville Syrjälä
2017-04-25  5:29     ` Vivi, Rodrigo
2017-04-25  7:08       ` Ander Conselvan De Oliveira
2017-04-06 19:15 ` [PATCH 59/67] drm/i915/cnl: Fix Cannonlake scaler mode programing Rodrigo Vivi
2017-04-24 18:11   ` Ville Syrjälä
2017-04-06 19:15 ` [PATCH 60/67] drm/i915/cnl: Enable fifo underrun for Cannonlake Rodrigo Vivi
2017-04-07  8:16   ` Mika Kahola
2017-04-06 19:15 ` [PATCH 61/67] drm/i915/cnl: Setup PAT Index Rodrigo Vivi
2017-04-06 19:15 ` [PATCH 62/67] drm/i915/cnl: Add support slice/subslice/eu configs Rodrigo Vivi
2017-04-06 19:15 ` [PATCH 63/67] drm/i915/cnl: Avoid ioremap_wc on Cannonlake as well Rodrigo Vivi
2017-04-06 19:16 ` [PATCH 64/67] drm/i915/cnl: WaThrottleEUPerfToAvoidTDBackPressure:cnl(pre-prod) Rodrigo Vivi
2017-09-06 21:55   ` Oscar Mateo
2017-04-06 19:16 ` [PATCH 65/67] drm/i915/cnl: Enable Audio Pin Buffer Rodrigo Vivi
2017-04-06 19:16 ` [PATCH 66/67] drm/i915/cnl: LSPCON support is gen9+ Rodrigo Vivi
2017-04-07  5:54   ` Sharma, Shashank
2017-04-06 19:16 ` [PATCH 67/67] drm/i915/cnl: Adjust min pixel rate Rodrigo Vivi
2017-04-06 20:12 ` ✗ Fi.CI.BAT: warning for series starting with [01/67] drm/i915/cnp: Introduce Cannonpoint PCH. (rev2) Patchwork
2017-04-07  1:13 ` ✗ Fi.CI.BAT: warning for series starting with [01/67] drm/i915/cnp: Introduce Cannonpoint PCH. (rev3) Patchwork
2017-04-13 17:53 ` [PATCH 01/67] drm/i915/cnp: Introduce Cannonpoint PCH Srivatsa, Anusha

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=f404cef3-df67-d35d-a041-bcdfc44d5307@linux.intel.com \
    --to=tvrtko.ursulin@linux.intel.com \
    --cc=intel-gfx@lists.freedesktop.org \
    --cc=rodrigo.vivi@intel.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).