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dkim=none (message not signed) header.d=none; lists.freedesktop.org; dmarc=none action=none header.from=intel.com; Received: from CO6PR11MB5634.namprd11.prod.outlook.com (2603:10b6:5:35d::20) by CO6PR11MB5601.namprd11.prod.outlook.com (2603:10b6:303:13d::7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4352.26; Wed, 28 Jul 2021 00:15:05 +0000 Received: from CO6PR11MB5634.namprd11.prod.outlook.com ([fe80::5d5e:b6bf:aafa:ecd4]) by CO6PR11MB5634.namprd11.prod.outlook.com ([fe80::5d5e:b6bf:aafa:ecd4%9]) with mapi id 15.20.4352.032; Wed, 28 Jul 2021 00:15:05 +0000 To: Matthew Brost References: <20210726190800.26762-1-vinay.belgaumkar@intel.com> <20210726190800.26762-12-vinay.belgaumkar@intel.com> <20210727154014.GA47916@DUT151-ICLU.fm.intel.com> From: "Belgaumkar, Vinay" Message-ID: Date: Tue, 27 Jul 2021 17:15:02 -0700 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:78.0) Gecko/20100101 Firefox/78.0 Thunderbird/78.12.0 In-Reply-To: <20210727154014.GA47916@DUT151-ICLU.fm.intel.com> Content-Language: en-US X-ClientProxiedBy: BYAPR04CA0023.namprd04.prod.outlook.com (2603:10b6:a03:40::36) To CO6PR11MB5634.namprd11.prod.outlook.com (2603:10b6:5:35d::20) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from [192.168.1.71] (99.88.121.38) by BYAPR04CA0023.namprd04.prod.outlook.com (2603:10b6:a03:40::36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4373.17 via Frontend Transport; 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charset="us-ascii"; Format="flowed" Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On 7/27/2021 8:40 AM, Matthew Brost wrote: > On Mon, Jul 26, 2021 at 12:07:56PM -0700, Vinay Belgaumkar wrote: >> This interrupt is enabled during RPS initialization, and >> now needs to be done by SLPC code. It allows ARAT timer >> expiry interrupts to get forwarded to GuC. >> >> Signed-off-by: Vinay Belgaumkar >> --- >> drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 16 ++++++++++++++++ >> drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h | 2 ++ >> drivers/gpu/drm/i915/gt/uc/intel_uc.c | 8 ++++++++ >> 3 files changed, 26 insertions(+) >> >> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c >> index 995d3d4807a3..c79dba60b2e6 100644 >> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c >> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c >> @@ -392,6 +392,20 @@ int intel_guc_slpc_get_min_freq(struct intel_guc_slpc *slpc, u32 *val) >> return ret; >> } >> >> +void intel_guc_pm_intrmsk_enable(struct intel_gt *gt) >> +{ >> + u32 pm_intrmsk_mbz = 0; >> + >> + /* Allow GuC to receive ARAT timer expiry event. > > I've been berated for using comments like this this by other engineers. > I personally don't care at all (nor does checkpatch) but if you want to > avoid the wrath of others I'd change this to what I have below: > > /* > * Allow GuC to receive ARAT timer expiry event. > * This interrupt register is setup by RPS code > * when host based Turbo is enabled. > */ > > Same goes for comment below of same style. > > Either way, patch looks good to me. With that: > Reviewed-by: Matthew Brost Fixed. Thanks, Vinay. > >> + * This interrupt register is setup by RPS code >> + * when host based Turbo is enabled. >> + */ >> + pm_intrmsk_mbz |= ARAT_EXPIRED_INTRMSK; >> + >> + intel_uncore_rmw(gt->uncore, >> + GEN6_PMINTRMSK, pm_intrmsk_mbz, 0); >> +} >> + >> /* >> * intel_guc_slpc_enable() - Start SLPC >> * @slpc: pointer to intel_guc_slpc. >> @@ -439,6 +453,8 @@ int intel_guc_slpc_enable(struct intel_guc_slpc *slpc) >> >> slpc_query_task_state(slpc); >> >> + intel_guc_pm_intrmsk_enable(&i915->gt); >> + >> /* min and max frequency limits being used by SLPC */ >> drm_info(&i915->drm, "SLPC min freq: %u Mhz, max is %u Mhz\n", >> slpc_decode_min_freq(slpc), >> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h >> index d133c8020c16..f128143cc1d8 100644 >> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h >> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h >> @@ -9,6 +9,7 @@ >> #include "intel_guc_submission.h" >> #include "intel_guc_slpc_types.h" >> >> +struct intel_gt; >> struct drm_printer; >> >> static inline bool intel_guc_slpc_is_supported(struct intel_guc *guc) >> @@ -35,5 +36,6 @@ int intel_guc_slpc_set_min_freq(struct intel_guc_slpc *slpc, u32 val); >> int intel_guc_slpc_get_max_freq(struct intel_guc_slpc *slpc, u32 *val); >> int intel_guc_slpc_get_min_freq(struct intel_guc_slpc *slpc, u32 *val); >> int intel_guc_slpc_info(struct intel_guc_slpc *slpc, struct drm_printer *p); >> +void intel_guc_pm_intrmsk_enable(struct intel_gt *gt); >> >> #endif >> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c b/drivers/gpu/drm/i915/gt/uc/intel_uc.c >> index b98c14f8c229..9238bc076605 100644 >> --- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c >> +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c >> @@ -652,6 +652,7 @@ void intel_uc_suspend(struct intel_uc *uc) >> static int __uc_resume(struct intel_uc *uc, bool enable_communication) >> { >> struct intel_guc *guc = &uc->guc; >> + struct intel_gt *gt = guc_to_gt(guc); >> int err; >> >> if (!intel_guc_is_fw_running(guc)) >> @@ -663,6 +664,13 @@ static int __uc_resume(struct intel_uc *uc, bool enable_communication) >> if (enable_communication) >> guc_enable_communication(guc); >> >> + /* If we are only resuming GuC communication but not reloading >> + * GuC, we need to ensure the ARAT timer interrupt is enabled >> + * again. In case of GuC reload, it is enabled during SLPC enable. >> + */ >> + if (enable_communication && intel_uc_uses_guc_slpc(uc)) >> + intel_guc_pm_intrmsk_enable(gt); >> + >> err = intel_guc_resume(guc); >> if (err) { >> DRM_DEBUG_DRIVER("Failed to resume GuC, err=%d", err); >> -- >> 2.25.0 >> _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx