* [PATCH 0/2] gen 9 h/w w/a cleanup
@ 2015-02-06 11:30 Nick Hoath
2015-02-06 11:30 ` [PATCH 1/2] drm/i915: gen 9 h/w w/a Fix stepping check Nick Hoath
2015-02-06 11:30 ` [PATCH 2/2] drm/i915: gen 9 h/w w/a (WaEnableForceRestoreInCtxtDescForVCS) Nick Hoath
0 siblings, 2 replies; 7+ messages in thread
From: Nick Hoath @ 2015-02-06 11:30 UTC (permalink / raw)
To: intel-gfx
Fix stepping check on WaDisableDgMirrorFixInHalfSliceChicken5, and
clean up WaEnableForceRestoreInCtxtDescForVCS patch.
Nick Hoath (2):
drm/i915: gen 9 h/w w/a Fix stepping check
drm/i915: gen 9 h/w w/a (WaEnableForceRestoreInCtxtDescForVCS)
drivers/gpu/drm/i915/intel_lrc.c | 15 ++++++++++++---
drivers/gpu/drm/i915/intel_ringbuffer.c | 3 ++-
2 files changed, 14 insertions(+), 4 deletions(-)
--
2.1.1
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^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH 1/2] drm/i915: gen 9 h/w w/a Fix stepping check
2015-02-06 11:30 [PATCH 0/2] gen 9 h/w w/a cleanup Nick Hoath
@ 2015-02-06 11:30 ` Nick Hoath
2015-02-06 11:52 ` Damien Lespiau
2015-02-06 11:30 ` [PATCH 2/2] drm/i915: gen 9 h/w w/a (WaEnableForceRestoreInCtxtDescForVCS) Nick Hoath
1 sibling, 1 reply; 7+ messages in thread
From: Nick Hoath @ 2015-02-06 11:30 UTC (permalink / raw)
To: intel-gfx
Fixed the stepping check on WaDisableDgMirrorFixInHalfSliceChicken5
to be for the correct SOC (Skylake)
Signed-off-by: Nick Hoath <nicholas.hoath@intel.com>
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 573b80f..fb71e33 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -886,7 +886,8 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC);
- if (INTEL_REVID(dev) == SKL_REVID_A0) {
+ if (INTEL_REVID(dev) >= SKL_REVID_A0 &&
+ INTEL_REVID(dev) <= SKL_REVID_B0) {
/*
* WaDisableDgMirrorFixInHalfSliceChicken5:skl
* This is a pre-production w/a.
--
2.1.1
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^ permalink raw reply related [flat|nested] 7+ messages in thread* Re: [PATCH 1/2] drm/i915: gen 9 h/w w/a Fix stepping check
2015-02-06 11:30 ` [PATCH 1/2] drm/i915: gen 9 h/w w/a Fix stepping check Nick Hoath
@ 2015-02-06 11:52 ` Damien Lespiau
2015-02-09 18:16 ` Daniel Vetter
0 siblings, 1 reply; 7+ messages in thread
From: Damien Lespiau @ 2015-02-06 11:52 UTC (permalink / raw)
To: Nick Hoath; +Cc: intel-gfx
On Fri, Feb 06, 2015 at 11:30:03AM +0000, Nick Hoath wrote:
> Fixed the stepping check on WaDisableDgMirrorFixInHalfSliceChicken5
> to be for the correct SOC (Skylake)
>
> Signed-off-by: Nick Hoath <nicholas.hoath@intel.com>
> ---
> drivers/gpu/drm/i915/intel_ringbuffer.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 573b80f..fb71e33 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -886,7 +886,8 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
> WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
> GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC);
>
> - if (INTEL_REVID(dev) == SKL_REVID_A0) {
> + if (INTEL_REVID(dev) >= SKL_REVID_A0 &&
> + INTEL_REVID(dev) <= SKL_REVID_B0) {
x >= 0 && x <= 1 looks really better as x == 0 || x == 1
Otherwise:
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
> /*
> * WaDisableDgMirrorFixInHalfSliceChicken5:skl
> * This is a pre-production w/a.
> --
> 2.1.1
>
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^ permalink raw reply [flat|nested] 7+ messages in thread* Re: [PATCH 1/2] drm/i915: gen 9 h/w w/a Fix stepping check
2015-02-06 11:52 ` Damien Lespiau
@ 2015-02-09 18:16 ` Daniel Vetter
0 siblings, 0 replies; 7+ messages in thread
From: Daniel Vetter @ 2015-02-09 18:16 UTC (permalink / raw)
To: Damien Lespiau; +Cc: intel-gfx
On Fri, Feb 06, 2015 at 11:52:42AM +0000, Damien Lespiau wrote:
> On Fri, Feb 06, 2015 at 11:30:03AM +0000, Nick Hoath wrote:
> > Fixed the stepping check on WaDisableDgMirrorFixInHalfSliceChicken5
> > to be for the correct SOC (Skylake)
> >
> > Signed-off-by: Nick Hoath <nicholas.hoath@intel.com>
> > ---
> > drivers/gpu/drm/i915/intel_ringbuffer.c | 3 ++-
> > 1 file changed, 2 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> > index 573b80f..fb71e33 100644
> > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> > @@ -886,7 +886,8 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
> > WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
> > GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC);
> >
> > - if (INTEL_REVID(dev) == SKL_REVID_A0) {
> > + if (INTEL_REVID(dev) >= SKL_REVID_A0 &&
> > + INTEL_REVID(dev) <= SKL_REVID_B0) {
>
> x >= 0 && x <= 1 looks really better as x == 0 || x == 1
for pre-production w/a I don't really care all that much how they look,
we'll remove them anyway in a few months or so. For production stuff I
prefer we stick to how we do gen checks:
- gen >= 5 (read as gen5+)
- gen < 6 (read as pre-gen5)
Consistency to avoid accidentaly off-by-one and it seems to match what
Bspec uses, too.
>
> Otherwise:
>
> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Both merged, thanks for patches&review.
-Daniel
>
> > /*
> > * WaDisableDgMirrorFixInHalfSliceChicken5:skl
> > * This is a pre-production w/a.
> > --
> > 2.1.1
> >
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH 2/2] drm/i915: gen 9 h/w w/a (WaEnableForceRestoreInCtxtDescForVCS)
2015-02-06 11:30 [PATCH 0/2] gen 9 h/w w/a cleanup Nick Hoath
2015-02-06 11:30 ` [PATCH 1/2] drm/i915: gen 9 h/w w/a Fix stepping check Nick Hoath
@ 2015-02-06 11:30 ` Nick Hoath
2015-02-06 11:58 ` Damien Lespiau
2015-02-07 13:35 ` shuang.he
1 sibling, 2 replies; 7+ messages in thread
From: Nick Hoath @ 2015-02-06 11:30 UTC (permalink / raw)
To: intel-gfx
Add:
WaEnableForceRestoreInCtxtDescForVCS
v2: Add stepping check.
v3: Fixed stepping check direction. Cleaned up indentation.
Signed-off-by: Nick Hoath <nicholas.hoath@intel.com>
---
drivers/gpu/drm/i915/intel_lrc.c | 15 ++++++++++++---
1 file changed, 12 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index a94346f..cc1c1a7 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -254,8 +254,10 @@ u32 intel_execlists_ctx_id(struct drm_i915_gem_object *ctx_obj)
return lrca >> 12;
}
-static uint64_t execlists_ctx_descriptor(struct drm_i915_gem_object *ctx_obj)
+static uint64_t execlists_ctx_descriptor(struct intel_engine_cs *ring,
+ struct drm_i915_gem_object *ctx_obj)
{
+ struct drm_device *dev = ring->dev;
uint64_t desc;
uint64_t lrca = i915_gem_obj_ggtt_offset(ctx_obj);
@@ -272,6 +274,13 @@ static uint64_t execlists_ctx_descriptor(struct drm_i915_gem_object *ctx_obj)
* signalling between Command Streamers */
/* desc |= GEN8_CTX_FORCE_RESTORE; */
+ /* WaEnableForceRestoreInCtxtDescForVCS:skl */
+ if (IS_GEN9(dev) &&
+ INTEL_REVID(dev) <= SKL_REVID_B0 &&
+ (ring->id == BCS || ring->id == VCS ||
+ ring->id == VECS || ring->id == VCS2))
+ desc |= GEN8_CTX_FORCE_RESTORE;
+
return desc;
}
@@ -286,13 +295,13 @@ static void execlists_elsp_write(struct intel_engine_cs *ring,
/* XXX: You must always write both descriptors in the order below. */
if (ctx_obj1)
- temp = execlists_ctx_descriptor(ctx_obj1);
+ temp = execlists_ctx_descriptor(ring, ctx_obj1);
else
temp = 0;
desc[1] = (u32)(temp >> 32);
desc[0] = (u32)temp;
- temp = execlists_ctx_descriptor(ctx_obj0);
+ temp = execlists_ctx_descriptor(ring, ctx_obj0);
desc[3] = (u32)(temp >> 32);
desc[2] = (u32)temp;
--
2.1.1
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^ permalink raw reply related [flat|nested] 7+ messages in thread* Re: [PATCH 2/2] drm/i915: gen 9 h/w w/a (WaEnableForceRestoreInCtxtDescForVCS)
2015-02-06 11:30 ` [PATCH 2/2] drm/i915: gen 9 h/w w/a (WaEnableForceRestoreInCtxtDescForVCS) Nick Hoath
@ 2015-02-06 11:58 ` Damien Lespiau
2015-02-07 13:35 ` shuang.he
1 sibling, 0 replies; 7+ messages in thread
From: Damien Lespiau @ 2015-02-06 11:58 UTC (permalink / raw)
To: Nick Hoath; +Cc: intel-gfx
On Fri, Feb 06, 2015 at 11:30:04AM +0000, Nick Hoath wrote:
> Add:
> WaEnableForceRestoreInCtxtDescForVCS
>
> v2: Add stepping check.
>
> v3: Fixed stepping check direction. Cleaned up indentation.
>
> Signed-off-by: Nick Hoath <nicholas.hoath@intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
--
Damien
> ---
> drivers/gpu/drm/i915/intel_lrc.c | 15 ++++++++++++---
> 1 file changed, 12 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index a94346f..cc1c1a7 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -254,8 +254,10 @@ u32 intel_execlists_ctx_id(struct drm_i915_gem_object *ctx_obj)
> return lrca >> 12;
> }
>
> -static uint64_t execlists_ctx_descriptor(struct drm_i915_gem_object *ctx_obj)
> +static uint64_t execlists_ctx_descriptor(struct intel_engine_cs *ring,
> + struct drm_i915_gem_object *ctx_obj)
> {
> + struct drm_device *dev = ring->dev;
> uint64_t desc;
> uint64_t lrca = i915_gem_obj_ggtt_offset(ctx_obj);
>
> @@ -272,6 +274,13 @@ static uint64_t execlists_ctx_descriptor(struct drm_i915_gem_object *ctx_obj)
> * signalling between Command Streamers */
> /* desc |= GEN8_CTX_FORCE_RESTORE; */
>
> + /* WaEnableForceRestoreInCtxtDescForVCS:skl */
> + if (IS_GEN9(dev) &&
> + INTEL_REVID(dev) <= SKL_REVID_B0 &&
> + (ring->id == BCS || ring->id == VCS ||
> + ring->id == VECS || ring->id == VCS2))
> + desc |= GEN8_CTX_FORCE_RESTORE;
> +
> return desc;
> }
>
> @@ -286,13 +295,13 @@ static void execlists_elsp_write(struct intel_engine_cs *ring,
>
> /* XXX: You must always write both descriptors in the order below. */
> if (ctx_obj1)
> - temp = execlists_ctx_descriptor(ctx_obj1);
> + temp = execlists_ctx_descriptor(ring, ctx_obj1);
> else
> temp = 0;
> desc[1] = (u32)(temp >> 32);
> desc[0] = (u32)temp;
>
> - temp = execlists_ctx_descriptor(ctx_obj0);
> + temp = execlists_ctx_descriptor(ring, ctx_obj0);
> desc[3] = (u32)(temp >> 32);
> desc[2] = (u32)temp;
>
> --
> 2.1.1
>
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^ permalink raw reply [flat|nested] 7+ messages in thread* Re: [PATCH 2/2] drm/i915: gen 9 h/w w/a (WaEnableForceRestoreInCtxtDescForVCS)
2015-02-06 11:30 ` [PATCH 2/2] drm/i915: gen 9 h/w w/a (WaEnableForceRestoreInCtxtDescForVCS) Nick Hoath
2015-02-06 11:58 ` Damien Lespiau
@ 2015-02-07 13:35 ` shuang.he
1 sibling, 0 replies; 7+ messages in thread
From: shuang.he @ 2015-02-07 13:35 UTC (permalink / raw)
To: shuang.he, ethan.gao, intel-gfx, nicholas.hoath
Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 5727
-------------------------------------Summary-------------------------------------
Platform Delta drm-intel-nightly Series Applied
PNV 283/283 283/283
ILK +1 310/319 311/319
SNB +1 342/346 343/346
IVB 380/384 380/384
BYT 296/296 296/296
HSW +1 423/428 424/428
BDW 318/333 318/333
-------------------------------------Detailed-------------------------------------
Platform Test drm-intel-nightly Series Applied
ILK igt_kms_flip_busy-flip-interruptible TIMEOUT(1, M37)PASS(1, M37) PASS(1, M37)
SNB igt_kms_pipe_crc_basic_read-crc-pipe-A DMESG_WARN(1, M22)PASS(1, M22) PASS(1, M22)
*HSW igt_gem_storedw_loop_vebox DMESG_WARN(2, M20) PASS(1, M20)
Note: You need to pay more attention to line start with '*'
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^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2015-02-09 18:15 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz follow: Atom feed
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2015-02-06 11:30 [PATCH 0/2] gen 9 h/w w/a cleanup Nick Hoath
2015-02-06 11:30 ` [PATCH 1/2] drm/i915: gen 9 h/w w/a Fix stepping check Nick Hoath
2015-02-06 11:52 ` Damien Lespiau
2015-02-09 18:16 ` Daniel Vetter
2015-02-06 11:30 ` [PATCH 2/2] drm/i915: gen 9 h/w w/a (WaEnableForceRestoreInCtxtDescForVCS) Nick Hoath
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2015-02-07 13:35 ` shuang.he
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