From: shuang.he@intel.com
To: shuang.he@intel.com, ethan.gao@intel.com,
intel-gfx@lists.freedesktop.org, ville.syrjala@linux.intel.com
Subject: Re: [PATCH 12/12] drm/i915: Enable the maxfifo PM5 mode when appropriate on CHV
Date: 10 Feb 2015 16:01:50 -0800 [thread overview]
Message-ID: <f539c7$k4n84p@fmsmga002.fm.intel.com> (raw)
In-Reply-To: <1423574909-1074-13-git-send-email-ville.syrjala@linux.intel.com>
Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 5748
-------------------------------------Summary-------------------------------------
Platform Delta drm-intel-nightly Series Applied
PNV +3 275/283 278/283
ILK +1-2 310/315 309/315
SNB +3 320/346 323/346
IVB -1 380/384 379/384
BYT 296/296 296/296
HSW +3 422/428 425/428
BDW 318/333 318/333
-------------------------------------Detailed-------------------------------------
Platform Test drm-intel-nightly Series Applied
PNV igt_gem_userptr_blits_coherency-sync CRASH(3, M7)PASS(2, M7) PASS(1, M7)
PNV igt_gem_userptr_blits_coherency-unsync CRASH(3, M7)PASS(3, M7) PASS(1, M7)
PNV igt_gem_userptr_blits_create-destroy-sync NRUN(1, M7)PASS(5, M7) PASS(1, M7)
PNV igt_gen3_render_tiledx_blits FAIL(2, M7)TIMEOUT(1, M7)PASS(3, M7) FAIL(1, M7)
ILK igt_gem_fenced_exec_thrash_no-spare-fences-busy-interruptible DMESG_WARN(1, M26)PASS(1, M26) DMESG_WARN(1, M26)
*ILK igt_gem_unfence_active_buffers PASS(3, M26) DMESG_WARN(1, M26)
*ILK igt_drv_suspend_forcewake DMESG_WARN(3, M26) PASS(1, M26)
*SNB igt_kms_flip_bo-too-big BLACKLIST(1, M35) PASS(1, M35)
*SNB igt_kms_flip_bo-too-big-interruptible BLACKLIST(1, M35) PASS(1, M35)
*SNB igt_kms_flip_event_leak NSPT(5, M35) PASS(1, M35)
IVB igt_gem_storedw_batches_loop_normal DMESG_WARN(1, M4)PASS(4, M4) DMESG_WARN(1, M4)
*HSW igt_kms_flip_bo-too-big BLACKLIST(1, M40) PASS(1, M40)
*HSW igt_kms_flip_bo-too-big-interruptible BLACKLIST(1, M40) PASS(1, M40)
HSW igt_kms_flip_plain-flip-fb-recreate-interruptible TIMEOUT(5, M40)PASS(2, M40) PASS(1, M40)
Note: You need to pay more attention to line start with '*'
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next prev parent reply other threads:[~2015-02-11 0:01 UTC|newest]
Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-02-10 13:28 [PATCH 00/12] drm/i915: Redo VLV/CHV watermark code ville.syrjala
2015-02-10 13:28 ` [PATCH 01/12] drm/i915: Reduce CHV DDL multiplier to 16/8 ville.syrjala
2015-02-27 17:36 ` Jesse Barnes
2015-02-27 18:02 ` Ville Syrjälä
[not found] ` <54F42A58.1020103@linux.intel.com>
2015-03-02 9:36 ` Arun R Murthy
2015-02-10 13:28 ` [PATCH 02/12] drm/i915: Kill DRAIN_LATENCY_PRECISION_* defines ville.syrjala
2015-02-27 17:38 ` Jesse Barnes
2015-02-27 18:06 ` Ville Syrjälä
2015-02-10 13:28 ` [PATCH 03/12] drm/i915: Simplify VLV drain latency computation ville.syrjala
2015-02-27 17:40 ` Jesse Barnes
2015-02-10 13:28 ` [PATCH 04/12] drm/i915: Hide VLV DDL precision handling ville.syrjala
2015-02-27 17:46 ` Jesse Barnes
2015-02-10 13:28 ` [PATCH 05/12] drm/i915: Reorganize VLV DDL setup ville.syrjala
2015-02-27 17:52 ` Jesse Barnes
2015-02-10 13:28 ` [PATCH 06/12] drm/i915: Pass plane to vlv_compute_drain_latency() ville.syrjala
2015-02-27 17:57 ` Jesse Barnes
2015-02-27 18:09 ` Ville Syrjälä
2015-02-27 20:37 ` Jesse Barnes
2015-03-02 14:44 ` Daniel Vetter
2015-03-02 14:49 ` Ville Syrjälä
2015-03-02 17:18 ` Daniel Vetter
2015-02-10 13:28 ` [PATCH 07/12] drm/i915: Read out display FIFO size on VLV/CHV ville.syrjala
2015-02-12 18:59 ` [PATCH v2 " ville.syrjala
2015-02-27 18:04 ` Jesse Barnes
2015-02-10 13:28 ` [PATCH 08/12] drm/i915: Make sure PND deadline mode is enabled " ville.syrjala
2015-02-27 20:38 ` Jesse Barnes
2015-02-27 20:48 ` Ville Syrjälä
2015-02-10 13:28 ` [PATCH 09/12] drm/i915: Rewrite VLV/CHV watermark code ville.syrjala
2015-03-05 17:22 ` Ville Syrjälä
2015-02-10 13:28 ` [PATCH 10/12] drm/i915: Support maxfifo with two planes on CHV ville.syrjala
2015-03-04 14:04 ` Purushothaman, Vijay A
2015-03-04 14:50 ` Ville Syrjälä
2015-02-10 13:28 ` [PATCH 11/12] drm/i915: Program PFI credits for VLV ville.syrjala
2015-03-04 14:25 ` Purushothaman, Vijay A
2015-03-04 15:06 ` Ville Syrjälä
2015-03-04 15:26 ` Ville Syrjälä
2015-02-10 13:28 ` [PATCH 12/12] drm/i915: Enable the maxfifo PM5 mode when appropriate on CHV ville.syrjala
2015-02-11 0:01 ` shuang.he [this message]
2015-02-26 19:01 ` [PATCH v2 " ville.syrjala
2015-03-04 14:28 ` [PATCH " Purushothaman, Vijay A
2015-03-04 15:07 ` Ville Syrjälä
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