[PATCH 0/8] Move PSR/Panel Replay sink data into intel_connector

[PATCH 0/8] Move PSR/Panel Replay sink data into intel_connector

[Jouni Högander]

This is a preparation patch set for MST Panel Replay.

In case of MST Panel Replay we may have several CRTCs on single
pipe. There CRTCs representing virtual devices within e.g. docking
station. All these virtual devices has their own DPCD registers
containing their Panel Replay capability information. These needs to
be taken into account when computing used Panel Replay state. Due to
this we can't continue having only sink capabilities stored in struct
intel_dp.

This patch set is moving Panel Replay capabilities into struct
intel_connector to make them available for Panel Replay CRTC state
computation.

Jouni Högander (8):
  drm/i915/psr: Add panel granularity information into intel_connector
  drm/i915/psr: Use SU granularity information available in
    intel_connector
  drm/i915/psr: Compute Panel Replay/Adaptive coexistence behavior
  drm/i915/psr: Move pr_dpcd and psr_dpcd to intel_connector
  drm/i915/psr: Clear pr_dpcd as well on disconnect
  drm/i915/psr: Move Panel Replay DSC sink support data to
    intel_connector
  drm/i915/psr: Move sink PSR and Panel Replay booleans to
    intel_connector
  drm/i915/psr: Move sink_sync_latency to intel_connector

 drivers/gpu/drm/i915/display/intel_alpm.c     |   6 +-
 .../drm/i915/display/intel_display_types.h    |  43 ++-
 drivers/gpu/drm/i915/display/intel_dp.c       |  11 +-
 drivers/gpu/drm/i915/display/intel_psr.c      | 283 ++++++++++--------
 drivers/gpu/drm/i915/display/intel_psr.h      |   2 +-
 5 files changed, 192 insertions(+), 153 deletions(-)

-- 
2.43.0

[PATCH 1/8] drm/i915/psr: Add panel granularity information into intel_connector

[Jouni Högander]

As a preparation for MST Panel Replay implementation add psr_caps and
panel_replay_caps structures into intel_connector. These are supposed to
contain all sink information related to PSR and Panel Replay.

As a first step in moving Panel Replay and PSR sink data add panel
granularity information into these newly added caps structures.

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_types.h | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 38702a9e0f508..f39d62aa99246 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -561,6 +561,16 @@ struct intel_connector {
 			} overall_throughput;
 			int max_line_width;
 		} dsc_branch_caps;
+
+		struct {
+			u16 su_w_granularity;
+			u16 su_y_granularity;
+		} panel_replay_caps;
+
+		struct {
+			u16 su_w_granularity;
+			u16 su_y_granularity;
+		} psr_caps;
 	} dp;
 
 	struct {
-- 
2.43.0

Re: [PATCH 1/8] drm/i915/psr: Add panel granularity information into intel_connector

[Imre Deak]

On Fri, Nov 21, 2025 at 01:16:48PM +0200, Jouni Högander wrote:
> As a preparation for MST Panel Replay implementation add psr_caps and
> panel_replay_caps structures into intel_connector. These are supposed to
> contain all sink information related to PSR and Panel Replay.
> 
> As a first step in moving Panel Replay and PSR sink data add panel
> granularity information into these newly added caps structures.
> 
> Signed-off-by: Jouni Högander <jouni.hogander@intel.com>

Reviewed-by: Imre Deak <imre.deak@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_display_types.h | 10 ++++++++++
>  1 file changed, 10 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 38702a9e0f508..f39d62aa99246 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -561,6 +561,16 @@ struct intel_connector {
>  			} overall_throughput;
>  			int max_line_width;
>  		} dsc_branch_caps;
> +
> +		struct {
> +			u16 su_w_granularity;
> +			u16 su_y_granularity;
> +		} panel_replay_caps;
> +
> +		struct {
> +			u16 su_w_granularity;
> +			u16 su_y_granularity;
> +		} psr_caps;
>  	} dp;
>  
>  	struct {
> -- 
> 2.43.0
> 

[PATCH 2/8] drm/i915/psr: Use SU granularity information available in intel_connector

[Jouni Högander]

Currently we are storing only one set of granularity information for panels
supporting both PSR and Panel Replay. It might be that in practice they are
always the same. As panel is informing own granularities for PSR and Panel
Replay let's use these instead of having only one set for both. This is
done by having intel_connector::psr_caps and panel_replay_caps both
containing granularity information.

This patch is also removing complexity of sharing granularity read between
PSR and Panel Replay.

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c  |   4 +-
 drivers/gpu/drm/i915/display/intel_psr.c | 139 +++++++++++------------
 drivers/gpu/drm/i915/display/intel_psr.h |   2 +-
 3 files changed, 69 insertions(+), 76 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 0ec82fcbcf48e..62808cd35f5f2 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -4562,7 +4562,7 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector
 	 * This has to be called after intel_dp->edp_dpcd is filled, PSR checks
 	 * for SET_POWER_CAPABLE bit in intel_dp->edp_dpcd[1]
 	 */
-	intel_psr_init_dpcd(intel_dp);
+	intel_psr_init_dpcd(intel_dp, connector);
 
 	intel_edp_set_sink_rates(intel_dp);
 	intel_dp_set_max_sink_lane_count(intel_dp);
@@ -6075,7 +6075,7 @@ intel_dp_detect(struct drm_connector *_connector,
 		connector->base.epoch_counter++;
 
 	if (!intel_dp_is_edp(intel_dp))
-		intel_psr_init_dpcd(intel_dp);
+		intel_psr_init_dpcd(intel_dp, connector);
 
 	intel_dp_detect_dsc_caps(intel_dp, connector);
 
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 00ac652809cca..4c5883bed612b 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -494,69 +494,26 @@ static u8 intel_dp_get_sink_sync_latency(struct intel_dp *intel_dp)
 	return val;
 }
 
-static u8 intel_dp_get_su_capability(struct intel_dp *intel_dp)
-{
-	u8 su_capability = 0;
-
-	if (intel_dp->psr.sink_panel_replay_su_support) {
-		if (drm_dp_dpcd_read_byte(&intel_dp->aux,
-					  DP_PANEL_REPLAY_CAP_CAPABILITY,
-					  &su_capability) < 0)
-			return 0;
-	} else {
-		su_capability = intel_dp->psr_dpcd[1];
-	}
-
-	return su_capability;
-}
-
-static unsigned int
-intel_dp_get_su_x_granularity_offset(struct intel_dp *intel_dp)
-{
-	return intel_dp->psr.sink_panel_replay_su_support ?
-		DP_PANEL_REPLAY_CAP_X_GRANULARITY :
-		DP_PSR2_SU_X_GRANULARITY;
-}
-
-static unsigned int
-intel_dp_get_su_y_granularity_offset(struct intel_dp *intel_dp)
-{
-	return intel_dp->psr.sink_panel_replay_su_support ?
-		DP_PANEL_REPLAY_CAP_Y_GRANULARITY :
-		DP_PSR2_SU_Y_GRANULARITY;
-}
-
-/*
- * Note: Bits related to granularity are same in panel replay and psr
- * registers. Rely on PSR definitions on these "common" bits.
- */
-static void intel_dp_get_su_granularity(struct intel_dp *intel_dp)
+static void _psr_compute_su_granularity(struct intel_dp *intel_dp,
+					struct intel_connector *connector)
 {
 	struct intel_display *display = to_intel_display(intel_dp);
 	ssize_t r;
 	u16 w;
 	u8 y;
 
-	/*
-	 * TODO: Do we need to take into account panel supporting both PSR and
-	 * Panel replay?
-	 */
-
 	/*
 	 * If sink don't have specific granularity requirements set legacy
 	 * ones.
 	 */
-	if (!(intel_dp_get_su_capability(intel_dp) &
-	      DP_PSR2_SU_GRANULARITY_REQUIRED)) {
+	if (!(intel_dp->psr_dpcd[1] & DP_PSR2_SU_GRANULARITY_REQUIRED)) {
 		/* As PSR2 HW sends full lines, we do not care about x granularity */
 		w = 4;
 		y = 4;
 		goto exit;
 	}
 
-	r = drm_dp_dpcd_read(&intel_dp->aux,
-			     intel_dp_get_su_x_granularity_offset(intel_dp),
-			     &w, 2);
+	r = drm_dp_dpcd_read(&intel_dp->aux, DP_PSR2_SU_X_GRANULARITY, &w, 2);
 	if (r != 2)
 		drm_dbg_kms(display->drm,
 			    "Unable to read selective update x granularity\n");
@@ -567,9 +524,7 @@ static void intel_dp_get_su_granularity(struct intel_dp *intel_dp)
 	if (r != 2 || w == 0)
 		w = 4;
 
-	r = drm_dp_dpcd_read(&intel_dp->aux,
-			     intel_dp_get_su_y_granularity_offset(intel_dp),
-			     &y, 1);
+	r = drm_dp_dpcd_read(&intel_dp->aux, DP_PSR2_SU_Y_GRANULARITY, &y, 1);
 	if (r != 1) {
 		drm_dbg_kms(display->drm,
 			    "Unable to read selective update y granularity\n");
@@ -579,8 +534,8 @@ static void intel_dp_get_su_granularity(struct intel_dp *intel_dp)
 		y = 1;
 
 exit:
-	intel_dp->psr.su_w_granularity = w;
-	intel_dp->psr.su_y_granularity = y;
+	connector->dp.psr_caps.su_w_granularity = w;
+	connector->dp.psr_caps.su_y_granularity = y;
 }
 
 static enum intel_panel_replay_dsc_support
@@ -621,7 +576,33 @@ static const char *panel_replay_dsc_support_str(enum intel_panel_replay_dsc_supp
 	};
 }
 
-static void _panel_replay_init_dpcd(struct intel_dp *intel_dp)
+static void _panel_replay_compute_su_granularity(struct intel_dp *intel_dp,
+						 struct intel_connector *connector)
+{
+	u16 w;
+	u8 y;
+
+	if (!(intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)] &
+	       DP_PANEL_REPLAY_SU_GRANULARITY_REQUIRED)) {
+		w = 4;
+		y = 4;
+		goto exit;
+	}
+
+	/*
+	 * Spec says that if the value read is 0 the default granularity should
+	 * be used instead.
+	 */
+	w = intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_X_GRANULARITY)] ? : 4;
+
+	y = intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_Y_GRANULARITY)] ? : 1;
+
+exit:
+	connector->dp.panel_replay_caps.su_w_granularity = w;
+	connector->dp.panel_replay_caps.su_y_granularity = y;
+}
+
+static void _panel_replay_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector)
 {
 	struct intel_display *display = to_intel_display(intel_dp);
 	int ret;
@@ -657,9 +638,12 @@ static void _panel_replay_init_dpcd(struct intel_dp *intel_dp)
 	intel_dp->psr.sink_panel_replay_support = true;
 
 	if (intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] &
-	    DP_PANEL_REPLAY_SU_SUPPORT)
+	    DP_PANEL_REPLAY_SU_SUPPORT) {
 		intel_dp->psr.sink_panel_replay_su_support = true;
 
+		_panel_replay_compute_su_granularity(intel_dp, connector);
+	}
+
 	intel_dp->psr.sink_panel_replay_dsc_support = compute_pr_dsc_support(intel_dp);
 
 	drm_dbg_kms(display->drm,
@@ -669,7 +653,7 @@ static void _panel_replay_init_dpcd(struct intel_dp *intel_dp)
 		    panel_replay_dsc_support_str(intel_dp->psr.sink_panel_replay_dsc_support));
 }
 
-static void _psr_init_dpcd(struct intel_dp *intel_dp)
+static void _psr_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector)
 {
 	struct intel_display *display = to_intel_display(intel_dp);
 	int ret;
@@ -722,17 +706,16 @@ static void _psr_init_dpcd(struct intel_dp *intel_dp)
 		drm_dbg_kms(display->drm, "PSR2 %ssupported\n",
 			    intel_dp->psr.sink_psr2_support ? "" : "not ");
 	}
+
+	if (intel_dp->psr.sink_psr2_support)
+		_psr_compute_su_granularity(intel_dp, connector);
 }
 
-void intel_psr_init_dpcd(struct intel_dp *intel_dp)
+void intel_psr_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector)
 {
-	_psr_init_dpcd(intel_dp);
+	_psr_init_dpcd(intel_dp, connector);
 
-	_panel_replay_init_dpcd(intel_dp);
-
-	if (intel_dp->psr.sink_psr2_support ||
-	    intel_dp->psr.sink_panel_replay_su_support)
-		intel_dp_get_su_granularity(intel_dp);
+	_panel_replay_init_dpcd(intel_dp, connector);
 }
 
 static void hsw_psr_setup_aux(struct intel_dp *intel_dp)
@@ -1311,24 +1294,32 @@ static bool intel_psr2_sel_fetch_config_valid(struct intel_dp *intel_dp,
 }
 
 static bool psr2_granularity_check(struct intel_dp *intel_dp,
-				   struct intel_crtc_state *crtc_state)
+				   struct intel_crtc_state *crtc_state,
+				   struct drm_connector_state *conn_state)
 {
 	struct intel_display *display = to_intel_display(intel_dp);
+	struct intel_connector *connector = to_intel_connector(conn_state->connector);
 	const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
 	const int crtc_hdisplay = crtc_state->hw.adjusted_mode.crtc_hdisplay;
 	const int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay;
 	u16 y_granularity = 0;
+	u16 sink_y_granularity = crtc_state->has_panel_replay ?
+		connector->dp.panel_replay_caps.su_y_granularity :
+		connector->dp.psr_caps.su_y_granularity;
+	u16 sink_w_granularity =  crtc_state->has_panel_replay ?
+		connector->dp.panel_replay_caps.su_w_granularity :
+		connector->dp.psr_caps.su_w_granularity;
 
 	/* PSR2 HW only send full lines so we only need to validate the width */
-	if (crtc_hdisplay % intel_dp->psr.su_w_granularity)
+	if (crtc_hdisplay % sink_w_granularity)
 		return false;
 
-	if (crtc_vdisplay % intel_dp->psr.su_y_granularity)
+	if (crtc_vdisplay % sink_y_granularity)
 		return false;
 
 	/* HW tracking is only aligned to 4 lines */
 	if (!crtc_state->enable_psr2_sel_fetch)
-		return intel_dp->psr.su_y_granularity == 4;
+		return sink_y_granularity == 4;
 
 	/*
 	 * adl_p and mtl platforms have 1 line granularity.
@@ -1336,11 +1327,11 @@ static bool psr2_granularity_check(struct intel_dp *intel_dp,
 	 * to match sink requirement if multiple of 4.
 	 */
 	if (display->platform.alderlake_p || DISPLAY_VER(display) >= 14)
-		y_granularity = intel_dp->psr.su_y_granularity;
-	else if (intel_dp->psr.su_y_granularity <= 2)
+		y_granularity = sink_y_granularity;
+	else if (sink_y_granularity <= 2)
 		y_granularity = 4;
-	else if ((intel_dp->psr.su_y_granularity % 4) == 0)
-		y_granularity = intel_dp->psr.su_y_granularity;
+	else if ((sink_y_granularity % 4) == 0)
+		y_granularity = sink_y_granularity;
 
 	if (y_granularity == 0 || crtc_vdisplay % y_granularity)
 		return false;
@@ -1628,7 +1619,8 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
 }
 
 static bool intel_sel_update_config_valid(struct intel_dp *intel_dp,
-					  struct intel_crtc_state *crtc_state)
+					  struct intel_crtc_state *crtc_state,
+					  struct drm_connector_state *conn_state)
 {
 	struct intel_display *display = to_intel_display(intel_dp);
 
@@ -1677,7 +1669,7 @@ static bool intel_sel_update_config_valid(struct intel_dp *intel_dp,
 		goto unsupported;
 	}
 
-	if (!psr2_granularity_check(intel_dp, crtc_state)) {
+	if (!psr2_granularity_check(intel_dp, crtc_state, conn_state)) {
 		drm_dbg_kms(display->drm,
 			    "Selective update not enabled, SU granularity not compatible\n");
 		goto unsupported;
@@ -1872,7 +1864,8 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
 	if (!crtc_state->has_psr)
 		return;
 
-	crtc_state->has_sel_update = intel_sel_update_config_valid(intel_dp, crtc_state);
+	crtc_state->has_sel_update = intel_sel_update_config_valid(intel_dp, crtc_state,
+								   conn_state);
 }
 
 void intel_psr_get_config(struct intel_encoder *encoder,
diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h
index 620b359288326..688ca3e73cdda 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.h
+++ b/drivers/gpu/drm/i915/display/intel_psr.h
@@ -28,7 +28,7 @@ struct intel_plane_state;
 bool intel_encoder_can_psr(struct intel_encoder *encoder);
 bool intel_psr_needs_aux_io_power(struct intel_encoder *encoder,
 				  const struct intel_crtc_state *crtc_state);
-void intel_psr_init_dpcd(struct intel_dp *intel_dp);
+void intel_psr_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector);
 void intel_psr_panel_replay_enable_sink(struct intel_dp *intel_dp);
 void intel_psr_pre_plane_update(struct intel_atomic_state *state,
 				struct intel_crtc *crtc);
-- 
2.43.0

Re: [PATCH 2/8] drm/i915/psr: Use SU granularity information available in intel_connector

[Imre Deak]

On Fri, Nov 21, 2025 at 01:16:49PM +0200, Jouni Högander wrote:
> Currently we are storing only one set of granularity information for panels
> supporting both PSR and Panel Replay. It might be that in practice they are
> always the same.

"in practice they could be different" would be what justifies the
changes. If you wanted to mention that they may be the same in practice,
it should be explained instead why tracking them separately still makes
sense.

> As panel is informing own granularities for PSR and Panel
> Replay let's use these instead of having only one set for both. This is
> done by having intel_connector::psr_caps and panel_replay_caps both
> containing granularity information.
> 
> This patch is also removing complexity of sharing granularity read between
> PSR and Panel Replay.
> 
> Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp.c  |   4 +-
>  drivers/gpu/drm/i915/display/intel_psr.c | 139 +++++++++++------------
>  drivers/gpu/drm/i915/display/intel_psr.h |   2 +-
>  3 files changed, 69 insertions(+), 76 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 0ec82fcbcf48e..62808cd35f5f2 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -4562,7 +4562,7 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector
>  	 * This has to be called after intel_dp->edp_dpcd is filled, PSR checks
>  	 * for SET_POWER_CAPABLE bit in intel_dp->edp_dpcd[1]
>  	 */
> -	intel_psr_init_dpcd(intel_dp);
> +	intel_psr_init_dpcd(intel_dp, connector);
>  
>  	intel_edp_set_sink_rates(intel_dp);
>  	intel_dp_set_max_sink_lane_count(intel_dp);
> @@ -6075,7 +6075,7 @@ intel_dp_detect(struct drm_connector *_connector,
>  		connector->base.epoch_counter++;
>  
>  	if (!intel_dp_is_edp(intel_dp))
> -		intel_psr_init_dpcd(intel_dp);
> +		intel_psr_init_dpcd(intel_dp, connector);
>  
>  	intel_dp_detect_dsc_caps(intel_dp, connector);
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 00ac652809cca..4c5883bed612b 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -494,69 +494,26 @@ static u8 intel_dp_get_sink_sync_latency(struct intel_dp *intel_dp)
>  	return val;
>  }
>  
> -static u8 intel_dp_get_su_capability(struct intel_dp *intel_dp)
> -{
> -	u8 su_capability = 0;
> -
> -	if (intel_dp->psr.sink_panel_replay_su_support) {
> -		if (drm_dp_dpcd_read_byte(&intel_dp->aux,
> -					  DP_PANEL_REPLAY_CAP_CAPABILITY,
> -					  &su_capability) < 0)
> -			return 0;
> -	} else {
> -		su_capability = intel_dp->psr_dpcd[1];
> -	}
> -
> -	return su_capability;
> -}
> -
> -static unsigned int
> -intel_dp_get_su_x_granularity_offset(struct intel_dp *intel_dp)
> -{
> -	return intel_dp->psr.sink_panel_replay_su_support ?
> -		DP_PANEL_REPLAY_CAP_X_GRANULARITY :
> -		DP_PSR2_SU_X_GRANULARITY;
> -}
> -
> -static unsigned int
> -intel_dp_get_su_y_granularity_offset(struct intel_dp *intel_dp)
> -{
> -	return intel_dp->psr.sink_panel_replay_su_support ?
> -		DP_PANEL_REPLAY_CAP_Y_GRANULARITY :
> -		DP_PSR2_SU_Y_GRANULARITY;
> -}
> -
> -/*
> - * Note: Bits related to granularity are same in panel replay and psr
> - * registers. Rely on PSR definitions on these "common" bits.
> - */
> -static void intel_dp_get_su_granularity(struct intel_dp *intel_dp)
> +static void _psr_compute_su_granularity(struct intel_dp *intel_dp,
> +					struct intel_connector *connector)
>  {
>  	struct intel_display *display = to_intel_display(intel_dp);
>  	ssize_t r;
>  	u16 w;

This should be changed to __le16 (even though not added in this patch).

>  	u8 y;
>  
> -	/*
> -	 * TODO: Do we need to take into account panel supporting both PSR and
> -	 * Panel replay?
> -	 */
> -
>  	/*
>  	 * If sink don't have specific granularity requirements set legacy
>  	 * ones.
>  	 */
> -	if (!(intel_dp_get_su_capability(intel_dp) &
> -	      DP_PSR2_SU_GRANULARITY_REQUIRED)) {
> +	if (!(intel_dp->psr_dpcd[1] & DP_PSR2_SU_GRANULARITY_REQUIRED)) {
>  		/* As PSR2 HW sends full lines, we do not care about x granularity */
>  		w = 4;
>  		y = 4;
>  		goto exit;
>  	}
>  
> -	r = drm_dp_dpcd_read(&intel_dp->aux,
> -			     intel_dp_get_su_x_granularity_offset(intel_dp),
> -			     &w, 2);
> +	r = drm_dp_dpcd_read(&intel_dp->aux, DP_PSR2_SU_X_GRANULARITY, &w, 2);

should be sizeof(w) instead of 2. (yes, not added in this patch, but
still)

>  	if (r != 2)
>  		drm_dbg_kms(display->drm,
>  			    "Unable to read selective update x granularity\n");
> @@ -567,9 +524,7 @@ static void intel_dp_get_su_granularity(struct intel_dp *intel_dp)
>  	if (r != 2 || w == 0)
>  		w = 4;
>  
> -	r = drm_dp_dpcd_read(&intel_dp->aux,
> -			     intel_dp_get_su_y_granularity_offset(intel_dp),
> -			     &y, 1);
> +	r = drm_dp_dpcd_read(&intel_dp->aux, DP_PSR2_SU_Y_GRANULARITY, &y, 1);
>  	if (r != 1) {
>  		drm_dbg_kms(display->drm,
>  			    "Unable to read selective update y granularity\n");
> @@ -579,8 +534,8 @@ static void intel_dp_get_su_granularity(struct intel_dp *intel_dp)
>  		y = 1;
>  
>  exit:
> -	intel_dp->psr.su_w_granularity = w;
> -	intel_dp->psr.su_y_granularity = y;
> +	connector->dp.psr_caps.su_w_granularity = w;

Should use le16_to_cpu(w) instead of w. w was used as-is already before
this change, however there is a related issue below, so I'd fix this one
as well in this patch/patchset.

> +	connector->dp.psr_caps.su_y_granularity = y;
>  }
>  
>  static enum intel_panel_replay_dsc_support
> @@ -621,7 +576,33 @@ static const char *panel_replay_dsc_support_str(enum intel_panel_replay_dsc_supp
>  	};
>  }
>  
> -static void _panel_replay_init_dpcd(struct intel_dp *intel_dp)
> +static void _panel_replay_compute_su_granularity(struct intel_dp *intel_dp,
> +						 struct intel_connector *connector)
> +{
> +	u16 w;
> +	u8 y;
> +
> +	if (!(intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)] &
> +	       DP_PANEL_REPLAY_SU_GRANULARITY_REQUIRED)) {
> +		w = 4;
> +		y = 4;
> +		goto exit;
> +	}
> +
> +	/*
> +	 * Spec says that if the value read is 0 the default granularity should
> +	 * be used instead.
> +	 */
> +	w = intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_X_GRANULARITY)] ? : 4;

The DP_PANEL_REPLAY_CAP_X_GRANULARITY field is 2 bytes in size. Here the
DPCD value should be converted (explicitly) with le16_to_cpu() as above.

> +
> +	y = intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_Y_GRANULARITY)] ? : 1;
> +
> +exit:
> +	connector->dp.panel_replay_caps.su_w_granularity = w;
> +	connector->dp.panel_replay_caps.su_y_granularity = y;
> +}
> +
> +static void _panel_replay_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector)
>  {
>  	struct intel_display *display = to_intel_display(intel_dp);
>  	int ret;
> @@ -657,9 +638,12 @@ static void _panel_replay_init_dpcd(struct intel_dp *intel_dp)
>  	intel_dp->psr.sink_panel_replay_support = true;
>  
>  	if (intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] &
> -	    DP_PANEL_REPLAY_SU_SUPPORT)
> +	    DP_PANEL_REPLAY_SU_SUPPORT) {
>  		intel_dp->psr.sink_panel_replay_su_support = true;
>  
> +		_panel_replay_compute_su_granularity(intel_dp, connector);
> +	}
> +
>  	intel_dp->psr.sink_panel_replay_dsc_support = compute_pr_dsc_support(intel_dp);
>  
>  	drm_dbg_kms(display->drm,
> @@ -669,7 +653,7 @@ static void _panel_replay_init_dpcd(struct intel_dp *intel_dp)
>  		    panel_replay_dsc_support_str(intel_dp->psr.sink_panel_replay_dsc_support));
>  }
>  
> -static void _psr_init_dpcd(struct intel_dp *intel_dp)
> +static void _psr_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector)
>  {
>  	struct intel_display *display = to_intel_display(intel_dp);
>  	int ret;
> @@ -722,17 +706,16 @@ static void _psr_init_dpcd(struct intel_dp *intel_dp)
>  		drm_dbg_kms(display->drm, "PSR2 %ssupported\n",
>  			    intel_dp->psr.sink_psr2_support ? "" : "not ");
>  	}
> +
> +	if (intel_dp->psr.sink_psr2_support)
> +		_psr_compute_su_granularity(intel_dp, connector);
>  }
>  
> -void intel_psr_init_dpcd(struct intel_dp *intel_dp)
> +void intel_psr_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector)
>  {
> -	_psr_init_dpcd(intel_dp);
> +	_psr_init_dpcd(intel_dp, connector);
>  
> -	_panel_replay_init_dpcd(intel_dp);
> -
> -	if (intel_dp->psr.sink_psr2_support ||
> -	    intel_dp->psr.sink_panel_replay_su_support)
> -		intel_dp_get_su_granularity(intel_dp);
> +	_panel_replay_init_dpcd(intel_dp, connector);
>  }
>  
>  static void hsw_psr_setup_aux(struct intel_dp *intel_dp)
> @@ -1311,24 +1294,32 @@ static bool intel_psr2_sel_fetch_config_valid(struct intel_dp *intel_dp,
>  }
>  
>  static bool psr2_granularity_check(struct intel_dp *intel_dp,
> -				   struct intel_crtc_state *crtc_state)
> +				   struct intel_crtc_state *crtc_state,
> +				   struct drm_connector_state *conn_state)

Nit: I'd keep the parameter list as short as possible, by dropping
intel_dp and getting it from the connector with intel_attached_dp() in
this function.

>  {
>  	struct intel_display *display = to_intel_display(intel_dp);
> +	struct intel_connector *connector = to_intel_connector(conn_state->connector);
>  	const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
>  	const int crtc_hdisplay = crtc_state->hw.adjusted_mode.crtc_hdisplay;
>  	const int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay;
>  	u16 y_granularity = 0;
> +	u16 sink_y_granularity = crtc_state->has_panel_replay ?
> +		connector->dp.panel_replay_caps.su_y_granularity :
> +		connector->dp.psr_caps.su_y_granularity;
> +	u16 sink_w_granularity =  crtc_state->has_panel_replay ?
> +		connector->dp.panel_replay_caps.su_w_granularity :
> +		connector->dp.psr_caps.su_w_granularity;
>  
>  	/* PSR2 HW only send full lines so we only need to validate the width */
> -	if (crtc_hdisplay % intel_dp->psr.su_w_granularity)
> +	if (crtc_hdisplay % sink_w_granularity)
>  		return false;
>  
> -	if (crtc_vdisplay % intel_dp->psr.su_y_granularity)
> +	if (crtc_vdisplay % sink_y_granularity)
>  		return false;
>  
>  	/* HW tracking is only aligned to 4 lines */
>  	if (!crtc_state->enable_psr2_sel_fetch)
> -		return intel_dp->psr.su_y_granularity == 4;
> +		return sink_y_granularity == 4;
>  
>  	/*
>  	 * adl_p and mtl platforms have 1 line granularity.
> @@ -1336,11 +1327,11 @@ static bool psr2_granularity_check(struct intel_dp *intel_dp,
>  	 * to match sink requirement if multiple of 4.
>  	 */
>  	if (display->platform.alderlake_p || DISPLAY_VER(display) >= 14)
> -		y_granularity = intel_dp->psr.su_y_granularity;
> -	else if (intel_dp->psr.su_y_granularity <= 2)
> +		y_granularity = sink_y_granularity;
> +	else if (sink_y_granularity <= 2)
>  		y_granularity = 4;
> -	else if ((intel_dp->psr.su_y_granularity % 4) == 0)
> -		y_granularity = intel_dp->psr.su_y_granularity;
> +	else if ((sink_y_granularity % 4) == 0)
> +		y_granularity = sink_y_granularity;
>  
>  	if (y_granularity == 0 || crtc_vdisplay % y_granularity)
>  		return false;
> @@ -1628,7 +1619,8 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
>  }
>  
>  static bool intel_sel_update_config_valid(struct intel_dp *intel_dp,
> -					  struct intel_crtc_state *crtc_state)
> +					  struct intel_crtc_state *crtc_state,
> +					  struct drm_connector_state *conn_state)

Here as well I'd drop intel_dp.

With the above fixed:
Reviewed-by: Imre Deak <imre.deak@intel.com>

>  {
>  	struct intel_display *display = to_intel_display(intel_dp);
>  
> @@ -1677,7 +1669,7 @@ static bool intel_sel_update_config_valid(struct intel_dp *intel_dp,
>  		goto unsupported;
>  	}
>  
> -	if (!psr2_granularity_check(intel_dp, crtc_state)) {
> +	if (!psr2_granularity_check(intel_dp, crtc_state, conn_state)) {
>  		drm_dbg_kms(display->drm,
>  			    "Selective update not enabled, SU granularity not compatible\n");
>  		goto unsupported;
> @@ -1872,7 +1864,8 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
>  	if (!crtc_state->has_psr)
>  		return;
>  
> -	crtc_state->has_sel_update = intel_sel_update_config_valid(intel_dp, crtc_state);
> +	crtc_state->has_sel_update = intel_sel_update_config_valid(intel_dp, crtc_state,
> +								   conn_state);
>  }
>  
>  void intel_psr_get_config(struct intel_encoder *encoder,
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h
> index 620b359288326..688ca3e73cdda 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.h
> +++ b/drivers/gpu/drm/i915/display/intel_psr.h
> @@ -28,7 +28,7 @@ struct intel_plane_state;
>  bool intel_encoder_can_psr(struct intel_encoder *encoder);
>  bool intel_psr_needs_aux_io_power(struct intel_encoder *encoder,
>  				  const struct intel_crtc_state *crtc_state);
> -void intel_psr_init_dpcd(struct intel_dp *intel_dp);
> +void intel_psr_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector);
>  void intel_psr_panel_replay_enable_sink(struct intel_dp *intel_dp);
>  void intel_psr_pre_plane_update(struct intel_atomic_state *state,
>  				struct intel_crtc *crtc);
> -- 
> 2.43.0
> 

[PATCH 3/8] drm/i915/psr: Compute Panel Replay/Adaptive coexistence behavior

[Jouni Högander]

Currently we are checking Panel Replay capability DPCD register in
intel_alpm.c and writing PR_ALPM_CTL_ALLOW_LINK_OFF_BETWEEN_AS_SDP_AND_SU
and PR_ALPM_CTL_AS_SDP_TRANSMISSION_IN_ACTIVE_DISABLE in PR_ALPM_CTL
register base on the informaion. Instead of directly accessing
intel_dp->pr_dpcd compute the behavior during psr_compute_config and store
it in intel_crtc_state.

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
---
 drivers/gpu/drm/i915/display/intel_alpm.c     |  6 ++---
 .../drm/i915/display/intel_display_types.h    |  2 ++
 drivers/gpu/drm/i915/display/intel_psr.c      | 22 +++++++++++++++----
 3 files changed, 22 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
index 6372f533f65b5..7ce8c674bb030 100644
--- a/drivers/gpu/drm/i915/display/intel_alpm.c
+++ b/drivers/gpu/drm/i915/display/intel_alpm.c
@@ -326,11 +326,9 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp,
 		if (intel_dp->as_sdp_supported) {
 			u32 pr_alpm_ctl = PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_T1;
 
-			if (intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)] &
-			    DP_PANEL_REPLAY_LINK_OFF_SUPPORTED_IN_PR_AFTER_ADAPTIVE_SYNC_SDP)
+			if (crtc_state->link_off_after_as_sdp_when_pr_active)
 				pr_alpm_ctl |= PR_ALPM_CTL_ALLOW_LINK_OFF_BETWEEN_AS_SDP_AND_SU;
-			if (!(intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)] &
-						DP_PANEL_REPLAY_ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR))
+			if (crtc_state->disable_as_sdp_when_pr_active)
 				pr_alpm_ctl |= PR_ALPM_CTL_AS_SDP_TRANSMISSION_IN_ACTIVE_DISABLE;
 
 			intel_de_write(display, PR_ALPM_CTL(display, cpu_transcoder),
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index f39d62aa99246..d8a222689a35b 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1161,6 +1161,8 @@ struct intel_crtc_state {
 	bool enable_psr2_su_region_et;
 	bool req_psr2_sdp_prior_scanline;
 	bool has_panel_replay;
+	bool link_off_after_as_sdp_when_pr_active;
+	bool disable_as_sdp_when_pr_active;
 	bool wm_level_disabled;
 	bool pkg_c_latency_used;
 	/* Only used for state verification. */
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 4c5883bed612b..9d2ba39423826 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1715,10 +1715,21 @@ static bool _psr_compute_config(struct intel_dp *intel_dp,
 	return true;
 }
 
-static bool
-_panel_replay_compute_config(struct intel_dp *intel_dp,
-			     struct intel_crtc_state *crtc_state,
-			     const struct drm_connector_state *conn_state)
+static bool compute_link_off_after_as_sdp_when_pr_active(struct intel_dp *intel_dp)
+{
+	return (intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)] &
+		DP_PANEL_REPLAY_LINK_OFF_SUPPORTED_IN_PR_AFTER_ADAPTIVE_SYNC_SDP);
+}
+
+static bool compute_disable_as_sdp_when_pr_active(struct intel_dp *intel_dp)
+{
+	return !(intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)] &
+		 DP_PANEL_REPLAY_ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR);
+}
+
+static bool _panel_replay_compute_config(struct intel_dp *intel_dp,
+					 struct intel_crtc_state *crtc_state,
+					 const struct drm_connector_state *conn_state)
 {
 	struct intel_display *display = to_intel_display(intel_dp);
 	struct intel_connector *connector =
@@ -1747,6 +1758,9 @@ _panel_replay_compute_config(struct intel_dp *intel_dp,
 		return false;
 	}
 
+	crtc_state->link_off_after_as_sdp_when_pr_active = compute_link_off_after_as_sdp_when_pr_active(intel_dp);
+	crtc_state->disable_as_sdp_when_pr_active = compute_disable_as_sdp_when_pr_active(intel_dp);
+
 	if (!intel_dp_is_edp(intel_dp))
 		return true;
 
-- 
2.43.0

Re: [PATCH 3/8] drm/i915/psr: Compute Panel Replay/Adaptive coexistence behavior

[Jani Nikula]

On Fri, 21 Nov 2025, Jouni Högander <jouni.hogander@intel.com> wrote:
> Currently we are checking Panel Replay capability DPCD register in
> intel_alpm.c and writing PR_ALPM_CTL_ALLOW_LINK_OFF_BETWEEN_AS_SDP_AND_SU
> and PR_ALPM_CTL_AS_SDP_TRANSMISSION_IN_ACTIVE_DISABLE in PR_ALPM_CTL
> register base on the informaion. Instead of directly accessing
> intel_dp->pr_dpcd compute the behavior during psr_compute_config and store
> it in intel_crtc_state.
>
> Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_alpm.c     |  6 ++---
>  .../drm/i915/display/intel_display_types.h    |  2 ++
>  drivers/gpu/drm/i915/display/intel_psr.c      | 22 +++++++++++++++----
>  3 files changed, 22 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
> index 6372f533f65b5..7ce8c674bb030 100644
> --- a/drivers/gpu/drm/i915/display/intel_alpm.c
> +++ b/drivers/gpu/drm/i915/display/intel_alpm.c
> @@ -326,11 +326,9 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp,
>  		if (intel_dp->as_sdp_supported) {
>  			u32 pr_alpm_ctl = PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_T1;
>  
> -			if (intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)] &
> -			    DP_PANEL_REPLAY_LINK_OFF_SUPPORTED_IN_PR_AFTER_ADAPTIVE_SYNC_SDP)
> +			if (crtc_state->link_off_after_as_sdp_when_pr_active)
>  				pr_alpm_ctl |= PR_ALPM_CTL_ALLOW_LINK_OFF_BETWEEN_AS_SDP_AND_SU;
> -			if (!(intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)] &
> -						DP_PANEL_REPLAY_ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR))
> +			if (crtc_state->disable_as_sdp_when_pr_active)
>  				pr_alpm_ctl |= PR_ALPM_CTL_AS_SDP_TRANSMISSION_IN_ACTIVE_DISABLE;
>  
>  			intel_de_write(display, PR_ALPM_CTL(display, cpu_transcoder),
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index f39d62aa99246..d8a222689a35b 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1161,6 +1161,8 @@ struct intel_crtc_state {
>  	bool enable_psr2_su_region_et;
>  	bool req_psr2_sdp_prior_scanline;
>  	bool has_panel_replay;
> +	bool link_off_after_as_sdp_when_pr_active;
> +	bool disable_as_sdp_when_pr_active;
>  	bool wm_level_disabled;
>  	bool pkg_c_latency_used;

Side note, we really *really* should start adding more (anonymous)
sub-structs in intel_crtc_state to group things. This has gotten out of
hands.

>  	/* Only used for state verification. */
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 4c5883bed612b..9d2ba39423826 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -1715,10 +1715,21 @@ static bool _psr_compute_config(struct intel_dp *intel_dp,
>  	return true;
>  }
>  
> -static bool
> -_panel_replay_compute_config(struct intel_dp *intel_dp,
> -			     struct intel_crtc_state *crtc_state,
> -			     const struct drm_connector_state *conn_state)
> +static bool compute_link_off_after_as_sdp_when_pr_active(struct intel_dp *intel_dp)
> +{
> +	return (intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)] &
> +		DP_PANEL_REPLAY_LINK_OFF_SUPPORTED_IN_PR_AFTER_ADAPTIVE_SYNC_SDP);
> +}
> +
> +static bool compute_disable_as_sdp_when_pr_active(struct intel_dp *intel_dp)
> +{
> +	return !(intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)] &
> +		 DP_PANEL_REPLAY_ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR);
> +}
> +
> +static bool _panel_replay_compute_config(struct intel_dp *intel_dp,
> +					 struct intel_crtc_state *crtc_state,
> +					 const struct drm_connector_state *conn_state)
>  {
>  	struct intel_display *display = to_intel_display(intel_dp);
>  	struct intel_connector *connector =
> @@ -1747,6 +1758,9 @@ _panel_replay_compute_config(struct intel_dp *intel_dp,
>  		return false;
>  	}
>  
> +	crtc_state->link_off_after_as_sdp_when_pr_active = compute_link_off_after_as_sdp_when_pr_active(intel_dp);
> +	crtc_state->disable_as_sdp_when_pr_active = compute_disable_as_sdp_when_pr_active(intel_dp);
> +
>  	if (!intel_dp_is_edp(intel_dp))
>  		return true;

-- 
Jani Nikula, Intel

Re: [PATCH 3/8] drm/i915/psr: Compute Panel Replay/Adaptive coexistence behavior

[Imre Deak]

On Fri, Nov 21, 2025 at 01:16:50PM +0200, Jouni Högander wrote:
> Currently we are checking Panel Replay capability DPCD register in
> intel_alpm.c and writing PR_ALPM_CTL_ALLOW_LINK_OFF_BETWEEN_AS_SDP_AND_SU
> and PR_ALPM_CTL_AS_SDP_TRANSMISSION_IN_ACTIVE_DISABLE in PR_ALPM_CTL
> register base on the informaion. Instead of directly accessing
> intel_dp->pr_dpcd compute the behavior during psr_compute_config and store
> it in intel_crtc_state.
> 
> Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_alpm.c     |  6 ++---
>  .../drm/i915/display/intel_display_types.h    |  2 ++
>  drivers/gpu/drm/i915/display/intel_psr.c      | 22 +++++++++++++++----
>  3 files changed, 22 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
> index 6372f533f65b5..7ce8c674bb030 100644
> --- a/drivers/gpu/drm/i915/display/intel_alpm.c
> +++ b/drivers/gpu/drm/i915/display/intel_alpm.c
> @@ -326,11 +326,9 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp,
>  		if (intel_dp->as_sdp_supported) {
>  			u32 pr_alpm_ctl = PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_T1;
>  
> -			if (intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)] &
> -			    DP_PANEL_REPLAY_LINK_OFF_SUPPORTED_IN_PR_AFTER_ADAPTIVE_SYNC_SDP)
> +			if (crtc_state->link_off_after_as_sdp_when_pr_active)
>  				pr_alpm_ctl |= PR_ALPM_CTL_ALLOW_LINK_OFF_BETWEEN_AS_SDP_AND_SU;
> -			if (!(intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)] &
> -						DP_PANEL_REPLAY_ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR))
> +			if (crtc_state->disable_as_sdp_when_pr_active)
>  				pr_alpm_ctl |= PR_ALPM_CTL_AS_SDP_TRANSMISSION_IN_ACTIVE_DISABLE;
>  
>  			intel_de_write(display, PR_ALPM_CTL(display, cpu_transcoder),
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index f39d62aa99246..d8a222689a35b 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1161,6 +1161,8 @@ struct intel_crtc_state {
>  	bool enable_psr2_su_region_et;
>  	bool req_psr2_sdp_prior_scanline;
>  	bool has_panel_replay;
> +	bool link_off_after_as_sdp_when_pr_active;
> +	bool disable_as_sdp_when_pr_active;

I agree with Jani that moving the PSR/Panel Replay fields to a substruct
would make things clearer. That's a bigger change, so I presume it could
be also a follow-up.

>  	bool wm_level_disabled;
>  	bool pkg_c_latency_used;
>  	/* Only used for state verification. */
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 4c5883bed612b..9d2ba39423826 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -1715,10 +1715,21 @@ static bool _psr_compute_config(struct intel_dp *intel_dp,
>  	return true;
>  }
>  
> -static bool
> -_panel_replay_compute_config(struct intel_dp *intel_dp,
> -			     struct intel_crtc_state *crtc_state,
> -			     const struct drm_connector_state *conn_state)
> +static bool compute_link_off_after_as_sdp_when_pr_active(struct intel_dp *intel_dp)
> +{
> +	return (intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)] &
> +		DP_PANEL_REPLAY_LINK_OFF_SUPPORTED_IN_PR_AFTER_ADAPTIVE_SYNC_SDP);
> +}
> +
> +static bool compute_disable_as_sdp_when_pr_active(struct intel_dp *intel_dp)
> +{
> +	return !(intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)] &
> +		 DP_PANEL_REPLAY_ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR);
> +}

Nit: Aren't the above functions simple enough to inline them? Or do they
get more complicated later?

> +
> +static bool _panel_replay_compute_config(struct intel_dp *intel_dp,
> +					 struct intel_crtc_state *crtc_state,
> +					 const struct drm_connector_state *conn_state)

Nit: I'd drop intel_dp as mentioned earlier.

Regardless, the patch looks ok:
Reviewed-by: Imre Deak <imre.deak@intel.com>


>  {
>  	struct intel_display *display = to_intel_display(intel_dp);
>  	struct intel_connector *connector =
> @@ -1747,6 +1758,9 @@ _panel_replay_compute_config(struct intel_dp *intel_dp,
>  		return false;
>  	}
>  
> +	crtc_state->link_off_after_as_sdp_when_pr_active = compute_link_off_after_as_sdp_when_pr_active(intel_dp);
> +	crtc_state->disable_as_sdp_when_pr_active = compute_disable_as_sdp_when_pr_active(intel_dp);
> +
>  	if (!intel_dp_is_edp(intel_dp))
>  		return true;
>  
> -- 
> 2.43.0
> 

[PATCH 4/8] drm/i915/psr: Move pr_dpcd and psr_dpcd to intel_connector

[Jouni Högander]

As a preparation for MST Panel Replay we need to move Panel Replay sink
related data into intel_connector. Move pr_dpcd as well into
intel_connector. Generally this is more correct place for this data so move
psr_dpcd as well.

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
---
 .../drm/i915/display/intel_display_types.h    |  6 +-
 drivers/gpu/drm/i915/display/intel_psr.c      | 85 ++++++++++---------
 2 files changed, 49 insertions(+), 42 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index d8a222689a35b..8587d2c527f72 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -548,6 +548,9 @@ struct intel_connector {
 	struct {
 		struct drm_dp_aux *dsc_decompression_aux;
 		u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE];
+		u8 psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
+		u8 pr_dpcd[DP_PANEL_REPLAY_CAP_SIZE];
+#define INTEL_PR_DPCD_INDEX(pr_dpcd_register)	((pr_dpcd_register) - DP_PANEL_REPLAY_CAP_SUPPORT)
 		u8 fec_capability;
 
 		u8 dsc_hblank_expansion_quirk:1;
@@ -1768,9 +1771,6 @@ struct intel_dp {
 	bool needs_modeset_retry;
 	bool use_max_params;
 	u8 dpcd[DP_RECEIVER_CAP_SIZE];
-	u8 psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
-	u8 pr_dpcd[DP_PANEL_REPLAY_CAP_SIZE];
-#define INTEL_PR_DPCD_INDEX(pr_dpcd_register)	((pr_dpcd_register) - DP_PANEL_REPLAY_CAP_SUPPORT)
 
 	u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
 	u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 9d2ba39423826..b488be8c917dc 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -506,7 +506,7 @@ static void _psr_compute_su_granularity(struct intel_dp *intel_dp,
 	 * If sink don't have specific granularity requirements set legacy
 	 * ones.
 	 */
-	if (!(intel_dp->psr_dpcd[1] & DP_PSR2_SU_GRANULARITY_REQUIRED)) {
+	if (!(connector->dp.psr_dpcd[1] & DP_PSR2_SU_GRANULARITY_REQUIRED)) {
 		/* As PSR2 HW sends full lines, we do not care about x granularity */
 		w = 4;
 		y = 4;
@@ -539,12 +539,12 @@ static void _psr_compute_su_granularity(struct intel_dp *intel_dp,
 }
 
 static enum intel_panel_replay_dsc_support
-compute_pr_dsc_support(struct intel_dp *intel_dp)
+compute_pr_dsc_support(struct intel_connector *connector)
 {
 	u8 pr_dsc_mode;
 	u8 val;
 
-	val = intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)];
+	val = connector->dp.pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)];
 	pr_dsc_mode = REG_FIELD_GET8(DP_PANEL_REPLAY_DSC_DECODE_CAPABILITY_IN_PR_MASK, val);
 
 	switch (pr_dsc_mode) {
@@ -582,7 +582,7 @@ static void _panel_replay_compute_su_granularity(struct intel_dp *intel_dp,
 	u16 w;
 	u8 y;
 
-	if (!(intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)] &
+	if (!(connector->dp.pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)] &
 	       DP_PANEL_REPLAY_SU_GRANULARITY_REQUIRED)) {
 		w = 4;
 		y = 4;
@@ -593,9 +593,9 @@ static void _panel_replay_compute_su_granularity(struct intel_dp *intel_dp,
 	 * Spec says that if the value read is 0 the default granularity should
 	 * be used instead.
 	 */
-	w = intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_X_GRANULARITY)] ? : 4;
+	w = connector->dp.pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_X_GRANULARITY)] ? : 4;
 
-	y = intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_Y_GRANULARITY)] ? : 1;
+	y = connector->dp.pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_Y_GRANULARITY)] ? : 1;
 
 exit:
 	connector->dp.panel_replay_caps.su_w_granularity = w;
@@ -612,11 +612,11 @@ static void _panel_replay_init_dpcd(struct intel_dp *intel_dp, struct intel_conn
 		return;
 
 	ret = drm_dp_dpcd_read_data(&intel_dp->aux, DP_PANEL_REPLAY_CAP_SUPPORT,
-				    &intel_dp->pr_dpcd, sizeof(intel_dp->pr_dpcd));
+				    &connector->dp.pr_dpcd, sizeof(connector->dp.pr_dpcd));
 	if (ret < 0)
 		return;
 
-	if (!(intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] &
+	if (!(connector->dp.pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] &
 	      DP_PANEL_REPLAY_SUPPORT))
 		return;
 
@@ -627,7 +627,7 @@ static void _panel_replay_init_dpcd(struct intel_dp *intel_dp, struct intel_conn
 			return;
 		}
 
-		if (!(intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] &
+		if (!(connector->dp.pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] &
 		      DP_PANEL_REPLAY_EARLY_TRANSPORT_SUPPORT)) {
 			drm_dbg_kms(display->drm,
 				    "Panel doesn't support early transport, eDP Panel Replay not possible\n");
@@ -637,14 +637,14 @@ static void _panel_replay_init_dpcd(struct intel_dp *intel_dp, struct intel_conn
 
 	intel_dp->psr.sink_panel_replay_support = true;
 
-	if (intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] &
+	if (connector->dp.pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] &
 	    DP_PANEL_REPLAY_SU_SUPPORT) {
 		intel_dp->psr.sink_panel_replay_su_support = true;
 
 		_panel_replay_compute_su_granularity(intel_dp, connector);
 	}
 
-	intel_dp->psr.sink_panel_replay_dsc_support = compute_pr_dsc_support(intel_dp);
+	intel_dp->psr.sink_panel_replay_dsc_support = compute_pr_dsc_support(connector);
 
 	drm_dbg_kms(display->drm,
 		    "Panel replay %sis supported by panel (in DSC mode: %s)\n",
@@ -658,16 +658,16 @@ static void _psr_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *co
 	struct intel_display *display = to_intel_display(intel_dp);
 	int ret;
 
-	ret = drm_dp_dpcd_read_data(&intel_dp->aux, DP_PSR_SUPPORT, intel_dp->psr_dpcd,
-				    sizeof(intel_dp->psr_dpcd));
+	ret = drm_dp_dpcd_read_data(&intel_dp->aux, DP_PSR_SUPPORT, connector->dp.psr_dpcd,
+				    sizeof(connector->dp.psr_dpcd));
 	if (ret < 0)
 		return;
 
-	if (!intel_dp->psr_dpcd[0])
+	if (!connector->dp.psr_dpcd[0])
 		return;
 
 	drm_dbg_kms(display->drm, "eDP panel supports PSR version %x\n",
-		    intel_dp->psr_dpcd[0]);
+		    connector->dp.psr_dpcd[0]);
 
 	if (drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_NO_PSR)) {
 		drm_dbg_kms(display->drm,
@@ -686,8 +686,8 @@ static void _psr_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *co
 		intel_dp_get_sink_sync_latency(intel_dp);
 
 	if (DISPLAY_VER(display) >= 9 &&
-	    intel_dp->psr_dpcd[0] >= DP_PSR2_WITH_Y_COORD_IS_SUPPORTED) {
-		bool y_req = intel_dp->psr_dpcd[1] &
+	    connector->dp.psr_dpcd[0] >= DP_PSR2_WITH_Y_COORD_IS_SUPPORTED) {
+		bool y_req = connector->dp.psr_dpcd[1] &
 			     DP_PSR2_SU_Y_COORDINATE_REQUIRED;
 
 		/*
@@ -755,7 +755,8 @@ static void hsw_psr_setup_aux(struct intel_dp *intel_dp)
 		       aux_ctl);
 }
 
-static bool psr2_su_region_et_valid(struct intel_dp *intel_dp, bool panel_replay)
+static bool psr2_su_region_et_valid(struct intel_dp *intel_dp, struct intel_connector *connector,
+				    bool panel_replay)
 {
 	struct intel_display *display = to_intel_display(intel_dp);
 
@@ -764,9 +765,9 @@ static bool psr2_su_region_et_valid(struct intel_dp *intel_dp, bool panel_replay
 		return false;
 
 	return panel_replay ?
-		intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] &
+		connector->dp.pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] &
 		DP_PANEL_REPLAY_EARLY_TRANSPORT_SUPPORT :
-		intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_ET_SUPPORTED;
+		connector->dp.psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_ET_SUPPORTED;
 }
 
 static void _panel_replay_enable_sink(struct intel_dp *intel_dp,
@@ -1369,16 +1370,18 @@ static bool _compute_psr2_sdp_prior_scanline_indication(struct intel_dp *intel_d
 }
 
 static int intel_psr_entry_setup_frames(struct intel_dp *intel_dp,
+					struct drm_connector_state *conn_state,
 					const struct drm_display_mode *adjusted_mode)
 {
 	struct intel_display *display = to_intel_display(intel_dp);
-	int psr_setup_time = drm_dp_psr_setup_time(intel_dp->psr_dpcd);
+	struct intel_connector *connector = to_intel_connector(conn_state->connector);
+	int psr_setup_time = drm_dp_psr_setup_time(connector->dp.psr_dpcd);
 	int entry_setup_frames = 0;
 
 	if (psr_setup_time < 0) {
 		drm_dbg_kms(display->drm,
 			    "PSR condition failed: Invalid PSR setup time (0x%02x)\n",
-			    intel_dp->psr_dpcd[1]);
+			    connector->dp.psr_dpcd[1]);
 		return -ETIME;
 	}
 
@@ -1623,6 +1626,7 @@ static bool intel_sel_update_config_valid(struct intel_dp *intel_dp,
 					  struct drm_connector_state *conn_state)
 {
 	struct intel_display *display = to_intel_display(intel_dp);
+	struct intel_connector *connector = to_intel_connector(conn_state->connector);
 
 	if (HAS_PSR2_SEL_FETCH(display) &&
 	    !intel_psr2_sel_fetch_config_valid(intel_dp, crtc_state) &&
@@ -1676,7 +1680,7 @@ static bool intel_sel_update_config_valid(struct intel_dp *intel_dp,
 	}
 
 	crtc_state->enable_psr2_su_region_et =
-		psr2_su_region_et_valid(intel_dp, crtc_state->has_panel_replay);
+		psr2_su_region_et_valid(intel_dp, connector, crtc_state->has_panel_replay);
 
 	return true;
 
@@ -1686,7 +1690,8 @@ static bool intel_sel_update_config_valid(struct intel_dp *intel_dp,
 }
 
 static bool _psr_compute_config(struct intel_dp *intel_dp,
-				struct intel_crtc_state *crtc_state)
+				struct intel_crtc_state *crtc_state,
+				struct drm_connector_state *conn_state)
 {
 	struct intel_display *display = to_intel_display(intel_dp);
 	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
@@ -1701,7 +1706,7 @@ static bool _psr_compute_config(struct intel_dp *intel_dp,
 	if (crtc_state->vrr.enable)
 		return false;
 
-	entry_setup_frames = intel_psr_entry_setup_frames(intel_dp, adjusted_mode);
+	entry_setup_frames = intel_psr_entry_setup_frames(intel_dp, conn_state, adjusted_mode);
 
 	if (entry_setup_frames >= 0) {
 		intel_dp->psr.entry_setup_frames = entry_setup_frames;
@@ -1715,15 +1720,15 @@ static bool _psr_compute_config(struct intel_dp *intel_dp,
 	return true;
 }
 
-static bool compute_link_off_after_as_sdp_when_pr_active(struct intel_dp *intel_dp)
+static bool compute_link_off_after_as_sdp_when_pr_active(struct intel_connector *connector)
 {
-	return (intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)] &
+	return (connector->dp.pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)] &
 		DP_PANEL_REPLAY_LINK_OFF_SUPPORTED_IN_PR_AFTER_ADAPTIVE_SYNC_SDP);
 }
 
-static bool compute_disable_as_sdp_when_pr_active(struct intel_dp *intel_dp)
+static bool compute_disable_as_sdp_when_pr_active(struct intel_connector *connector)
 {
-	return !(intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)] &
+	return !(connector->dp.pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)] &
 		 DP_PANEL_REPLAY_ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR);
 }
 
@@ -1758,8 +1763,8 @@ static bool _panel_replay_compute_config(struct intel_dp *intel_dp,
 		return false;
 	}
 
-	crtc_state->link_off_after_as_sdp_when_pr_active = compute_link_off_after_as_sdp_when_pr_active(intel_dp);
-	crtc_state->disable_as_sdp_when_pr_active = compute_disable_as_sdp_when_pr_active(intel_dp);
+	crtc_state->link_off_after_as_sdp_when_pr_active = compute_link_off_after_as_sdp_when_pr_active(connector);
+	crtc_state->disable_as_sdp_when_pr_active = compute_disable_as_sdp_when_pr_active(connector);
 
 	if (!intel_dp_is_edp(intel_dp))
 		return true;
@@ -1873,7 +1878,7 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
 								    conn_state);
 
 	crtc_state->has_psr = crtc_state->has_panel_replay ? true :
-		_psr_compute_config(intel_dp, crtc_state);
+		_psr_compute_config(intel_dp, crtc_state, conn_state);
 
 	if (!crtc_state->has_psr)
 		return;
@@ -4123,6 +4128,7 @@ psr_source_status(struct intel_dp *intel_dp, struct seq_file *m)
 }
 
 static void intel_psr_sink_capability(struct intel_dp *intel_dp,
+				      struct intel_connector *connector,
 				      struct seq_file *m)
 {
 	struct intel_psr *psr = &intel_dp->psr;
@@ -4131,15 +4137,15 @@ static void intel_psr_sink_capability(struct intel_dp *intel_dp,
 		   str_yes_no(psr->sink_support));
 
 	if (psr->sink_support)
-		seq_printf(m, " [0x%02x]", intel_dp->psr_dpcd[0]);
-	if (intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_ET_SUPPORTED)
+		seq_printf(m, " [0x%02x]", connector->dp.psr_dpcd[0]);
+	if (connector->dp.psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_ET_SUPPORTED)
 		seq_printf(m, " (Early Transport)");
 	seq_printf(m, ", Panel Replay = %s", str_yes_no(psr->sink_panel_replay_support));
 	seq_printf(m, ", Panel Replay Selective Update = %s",
 		   str_yes_no(psr->sink_panel_replay_su_support));
 	seq_printf(m, ", Panel Replay DSC support = %s",
 		   panel_replay_dsc_support_str(psr->sink_panel_replay_dsc_support));
-	if (intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] &
+	if (connector->dp.pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] &
 	    DP_PANEL_REPLAY_EARLY_TRANSPORT_SUPPORT)
 		seq_printf(m, " (Early Transport)");
 	seq_printf(m, "\n");
@@ -4177,7 +4183,8 @@ static void intel_psr_print_mode(struct intel_dp *intel_dp,
 		seq_printf(m, "  %s\n", psr->no_psr_reason);
 }
 
-static int intel_psr_status(struct seq_file *m, struct intel_dp *intel_dp)
+static int intel_psr_status(struct seq_file *m, struct intel_dp *intel_dp,
+			    struct intel_connector *connector)
 {
 	struct intel_display *display = to_intel_display(intel_dp);
 	enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
@@ -4186,7 +4193,7 @@ static int intel_psr_status(struct seq_file *m, struct intel_dp *intel_dp)
 	bool enabled;
 	u32 val, psr2_ctl;
 
-	intel_psr_sink_capability(intel_dp, m);
+	intel_psr_sink_capability(intel_dp, connector, m);
 
 	if (!(psr->sink_support || psr->sink_panel_replay_support))
 		return 0;
@@ -4302,7 +4309,7 @@ static int i915_edp_psr_status_show(struct seq_file *m, void *data)
 	if (!intel_dp)
 		return -ENODEV;
 
-	return intel_psr_status(m, intel_dp);
+	return intel_psr_status(m, intel_dp, intel_dp->attached_connector);
 }
 DEFINE_SHOW_ATTRIBUTE(i915_edp_psr_status);
 
@@ -4436,7 +4443,7 @@ static int i915_psr_status_show(struct seq_file *m, void *data)
 	struct intel_connector *connector = m->private;
 	struct intel_dp *intel_dp = intel_attached_dp(connector);
 
-	return intel_psr_status(m, intel_dp);
+	return intel_psr_status(m, intel_dp, connector);
 }
 DEFINE_SHOW_ATTRIBUTE(i915_psr_status);
 
-- 
2.43.0

Re: [PATCH 4/8] drm/i915/psr: Move pr_dpcd and psr_dpcd to intel_connector

[Imre Deak]

On Fri, Nov 21, 2025 at 01:16:51PM +0200, Jouni Högander wrote:
> As a preparation for MST Panel Replay we need to move Panel Replay sink
> related data into intel_connector. Move pr_dpcd as well into
> intel_connector. Generally this is more correct place for this data so move
> psr_dpcd as well.
> 
> Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> ---
>  .../drm/i915/display/intel_display_types.h    |  6 +-
>  drivers/gpu/drm/i915/display/intel_psr.c      | 85 ++++++++++---------
>  2 files changed, 49 insertions(+), 42 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index d8a222689a35b..8587d2c527f72 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -548,6 +548,9 @@ struct intel_connector {
>  	struct {
>  		struct drm_dp_aux *dsc_decompression_aux;
>  		u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE];
> +		u8 psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];

I'd add this to the psr_caps substruct you added earlier in the
patchset. Yes, the dsc fields could be also in their own substruct, but
all the PSR / Panel Replay could be added accordingly already now.

> +		u8 pr_dpcd[DP_PANEL_REPLAY_CAP_SIZE];
> +#define INTEL_PR_DPCD_INDEX(pr_dpcd_register)	((pr_dpcd_register) - DP_PANEL_REPLAY_CAP_SUPPORT)

Similarly, I'd add this to the panel_replay_caps substruct.

>  		u8 fec_capability;
>  
>  		u8 dsc_hblank_expansion_quirk:1;
> @@ -1768,9 +1771,6 @@ struct intel_dp {
>  	bool needs_modeset_retry;
>  	bool use_max_params;
>  	u8 dpcd[DP_RECEIVER_CAP_SIZE];
> -	u8 psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
> -	u8 pr_dpcd[DP_PANEL_REPLAY_CAP_SIZE];
> -#define INTEL_PR_DPCD_INDEX(pr_dpcd_register)	((pr_dpcd_register) - DP_PANEL_REPLAY_CAP_SUPPORT)
>  
>  	u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
>  	u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 9d2ba39423826..b488be8c917dc 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -506,7 +506,7 @@ static void _psr_compute_su_granularity(struct intel_dp *intel_dp,
>  	 * If sink don't have specific granularity requirements set legacy
>  	 * ones.
>  	 */
> -	if (!(intel_dp->psr_dpcd[1] & DP_PSR2_SU_GRANULARITY_REQUIRED)) {
> +	if (!(connector->dp.psr_dpcd[1] & DP_PSR2_SU_GRANULARITY_REQUIRED)) {
>  		/* As PSR2 HW sends full lines, we do not care about x granularity */
>  		w = 4;
>  		y = 4;
> @@ -539,12 +539,12 @@ static void _psr_compute_su_granularity(struct intel_dp *intel_dp,
>  }
>  
>  static enum intel_panel_replay_dsc_support
> -compute_pr_dsc_support(struct intel_dp *intel_dp)
> +compute_pr_dsc_support(struct intel_connector *connector)
>  {
>  	u8 pr_dsc_mode;
>  	u8 val;
>  
> -	val = intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)];
> +	val = connector->dp.pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)];
>  	pr_dsc_mode = REG_FIELD_GET8(DP_PANEL_REPLAY_DSC_DECODE_CAPABILITY_IN_PR_MASK, val);
>  
>  	switch (pr_dsc_mode) {
> @@ -582,7 +582,7 @@ static void _panel_replay_compute_su_granularity(struct intel_dp *intel_dp,
>  	u16 w;
>  	u8 y;
>  
> -	if (!(intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)] &
> +	if (!(connector->dp.pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)] &
>  	       DP_PANEL_REPLAY_SU_GRANULARITY_REQUIRED)) {
>  		w = 4;
>  		y = 4;
> @@ -593,9 +593,9 @@ static void _panel_replay_compute_su_granularity(struct intel_dp *intel_dp,
>  	 * Spec says that if the value read is 0 the default granularity should
>  	 * be used instead.
>  	 */
> -	w = intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_X_GRANULARITY)] ? : 4;
> +	w = connector->dp.pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_X_GRANULARITY)] ? : 4;

This needs the field size and le16_to_cpu() fix mentioned earlier.

>  
> -	y = intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_Y_GRANULARITY)] ? : 1;
> +	y = connector->dp.pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_Y_GRANULARITY)] ? : 1;
>  
>  exit:
>  	connector->dp.panel_replay_caps.su_w_granularity = w;
> @@ -612,11 +612,11 @@ static void _panel_replay_init_dpcd(struct intel_dp *intel_dp, struct intel_conn
>  		return;
>  
>  	ret = drm_dp_dpcd_read_data(&intel_dp->aux, DP_PANEL_REPLAY_CAP_SUPPORT,
> -				    &intel_dp->pr_dpcd, sizeof(intel_dp->pr_dpcd));
> +				    &connector->dp.pr_dpcd, sizeof(connector->dp.pr_dpcd));
>  	if (ret < 0)
>  		return;
>  
> -	if (!(intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] &
> +	if (!(connector->dp.pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] &
>  	      DP_PANEL_REPLAY_SUPPORT))
>  		return;
>  
> @@ -627,7 +627,7 @@ static void _panel_replay_init_dpcd(struct intel_dp *intel_dp, struct intel_conn
>  			return;
>  		}
>  
> -		if (!(intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] &
> +		if (!(connector->dp.pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] &
>  		      DP_PANEL_REPLAY_EARLY_TRANSPORT_SUPPORT)) {
>  			drm_dbg_kms(display->drm,
>  				    "Panel doesn't support early transport, eDP Panel Replay not possible\n");
> @@ -637,14 +637,14 @@ static void _panel_replay_init_dpcd(struct intel_dp *intel_dp, struct intel_conn
>  
>  	intel_dp->psr.sink_panel_replay_support = true;
>  
> -	if (intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] &
> +	if (connector->dp.pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] &
>  	    DP_PANEL_REPLAY_SU_SUPPORT) {
>  		intel_dp->psr.sink_panel_replay_su_support = true;
>  
>  		_panel_replay_compute_su_granularity(intel_dp, connector);
>  	}
>  
> -	intel_dp->psr.sink_panel_replay_dsc_support = compute_pr_dsc_support(intel_dp);
> +	intel_dp->psr.sink_panel_replay_dsc_support = compute_pr_dsc_support(connector);
>  
>  	drm_dbg_kms(display->drm,
>  		    "Panel replay %sis supported by panel (in DSC mode: %s)\n",
> @@ -658,16 +658,16 @@ static void _psr_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *co
>  	struct intel_display *display = to_intel_display(intel_dp);
>  	int ret;
>  
> -	ret = drm_dp_dpcd_read_data(&intel_dp->aux, DP_PSR_SUPPORT, intel_dp->psr_dpcd,
> -				    sizeof(intel_dp->psr_dpcd));
> +	ret = drm_dp_dpcd_read_data(&intel_dp->aux, DP_PSR_SUPPORT, connector->dp.psr_dpcd,
> +				    sizeof(connector->dp.psr_dpcd));
>  	if (ret < 0)
>  		return;
>  
> -	if (!intel_dp->psr_dpcd[0])
> +	if (!connector->dp.psr_dpcd[0])
>  		return;
>  
>  	drm_dbg_kms(display->drm, "eDP panel supports PSR version %x\n",
> -		    intel_dp->psr_dpcd[0]);
> +		    connector->dp.psr_dpcd[0]);
>  
>  	if (drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_NO_PSR)) {
>  		drm_dbg_kms(display->drm,
> @@ -686,8 +686,8 @@ static void _psr_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *co
>  		intel_dp_get_sink_sync_latency(intel_dp);
>  
>  	if (DISPLAY_VER(display) >= 9 &&
> -	    intel_dp->psr_dpcd[0] >= DP_PSR2_WITH_Y_COORD_IS_SUPPORTED) {
> -		bool y_req = intel_dp->psr_dpcd[1] &
> +	    connector->dp.psr_dpcd[0] >= DP_PSR2_WITH_Y_COORD_IS_SUPPORTED) {
> +		bool y_req = connector->dp.psr_dpcd[1] &
>  			     DP_PSR2_SU_Y_COORDINATE_REQUIRED;
>  
>  		/*
> @@ -755,7 +755,8 @@ static void hsw_psr_setup_aux(struct intel_dp *intel_dp)
>  		       aux_ctl);
>  }
>  
> -static bool psr2_su_region_et_valid(struct intel_dp *intel_dp, bool panel_replay)
> +static bool psr2_su_region_et_valid(struct intel_dp *intel_dp, struct intel_connector *connector,
> +				    bool panel_replay)

Nit: intel_dp could be dropped here. Similarly in the functions below to
which you need to pass connector or conn_state.

Regardless of the nit, the patch looks ok:
Reviewed-by: Imre Deak <imre.deak@intel.com>

>  {
>  	struct intel_display *display = to_intel_display(intel_dp);
>  
> @@ -764,9 +765,9 @@ static bool psr2_su_region_et_valid(struct intel_dp *intel_dp, bool panel_replay
>  		return false;
>  
>  	return panel_replay ?
> -		intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] &
> +		connector->dp.pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] &
>  		DP_PANEL_REPLAY_EARLY_TRANSPORT_SUPPORT :
> -		intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_ET_SUPPORTED;
> +		connector->dp.psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_ET_SUPPORTED;
>  }
>  
>  static void _panel_replay_enable_sink(struct intel_dp *intel_dp,
> @@ -1369,16 +1370,18 @@ static bool _compute_psr2_sdp_prior_scanline_indication(struct intel_dp *intel_d
>  }
>  
>  static int intel_psr_entry_setup_frames(struct intel_dp *intel_dp,
> +					struct drm_connector_state *conn_state,
>  					const struct drm_display_mode *adjusted_mode)
>  {
>  	struct intel_display *display = to_intel_display(intel_dp);
> -	int psr_setup_time = drm_dp_psr_setup_time(intel_dp->psr_dpcd);
> +	struct intel_connector *connector = to_intel_connector(conn_state->connector);
> +	int psr_setup_time = drm_dp_psr_setup_time(connector->dp.psr_dpcd);
>  	int entry_setup_frames = 0;
>  
>  	if (psr_setup_time < 0) {
>  		drm_dbg_kms(display->drm,
>  			    "PSR condition failed: Invalid PSR setup time (0x%02x)\n",
> -			    intel_dp->psr_dpcd[1]);
> +			    connector->dp.psr_dpcd[1]);
>  		return -ETIME;
>  	}
>  
> @@ -1623,6 +1626,7 @@ static bool intel_sel_update_config_valid(struct intel_dp *intel_dp,
>  					  struct drm_connector_state *conn_state)
>  {
>  	struct intel_display *display = to_intel_display(intel_dp);
> +	struct intel_connector *connector = to_intel_connector(conn_state->connector);
>  
>  	if (HAS_PSR2_SEL_FETCH(display) &&
>  	    !intel_psr2_sel_fetch_config_valid(intel_dp, crtc_state) &&
> @@ -1676,7 +1680,7 @@ static bool intel_sel_update_config_valid(struct intel_dp *intel_dp,
>  	}
>  
>  	crtc_state->enable_psr2_su_region_et =
> -		psr2_su_region_et_valid(intel_dp, crtc_state->has_panel_replay);
> +		psr2_su_region_et_valid(intel_dp, connector, crtc_state->has_panel_replay);
>  
>  	return true;
>  
> @@ -1686,7 +1690,8 @@ static bool intel_sel_update_config_valid(struct intel_dp *intel_dp,
>  }
>  
>  static bool _psr_compute_config(struct intel_dp *intel_dp,
> -				struct intel_crtc_state *crtc_state)
> +				struct intel_crtc_state *crtc_state,
> +				struct drm_connector_state *conn_state)
>  {
>  	struct intel_display *display = to_intel_display(intel_dp);
>  	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
> @@ -1701,7 +1706,7 @@ static bool _psr_compute_config(struct intel_dp *intel_dp,
>  	if (crtc_state->vrr.enable)
>  		return false;
>  
> -	entry_setup_frames = intel_psr_entry_setup_frames(intel_dp, adjusted_mode);
> +	entry_setup_frames = intel_psr_entry_setup_frames(intel_dp, conn_state, adjusted_mode);
>  
>  	if (entry_setup_frames >= 0) {
>  		intel_dp->psr.entry_setup_frames = entry_setup_frames;
> @@ -1715,15 +1720,15 @@ static bool _psr_compute_config(struct intel_dp *intel_dp,
>  	return true;
>  }
>  
> -static bool compute_link_off_after_as_sdp_when_pr_active(struct intel_dp *intel_dp)
> +static bool compute_link_off_after_as_sdp_when_pr_active(struct intel_connector *connector)
>  {
> -	return (intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)] &
> +	return (connector->dp.pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)] &
>  		DP_PANEL_REPLAY_LINK_OFF_SUPPORTED_IN_PR_AFTER_ADAPTIVE_SYNC_SDP);
>  }
>  
> -static bool compute_disable_as_sdp_when_pr_active(struct intel_dp *intel_dp)
> +static bool compute_disable_as_sdp_when_pr_active(struct intel_connector *connector)
>  {
> -	return !(intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)] &
> +	return !(connector->dp.pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)] &
>  		 DP_PANEL_REPLAY_ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR);
>  }
>  
> @@ -1758,8 +1763,8 @@ static bool _panel_replay_compute_config(struct intel_dp *intel_dp,
>  		return false;
>  	}
>  
> -	crtc_state->link_off_after_as_sdp_when_pr_active = compute_link_off_after_as_sdp_when_pr_active(intel_dp);
> -	crtc_state->disable_as_sdp_when_pr_active = compute_disable_as_sdp_when_pr_active(intel_dp);
> +	crtc_state->link_off_after_as_sdp_when_pr_active = compute_link_off_after_as_sdp_when_pr_active(connector);
> +	crtc_state->disable_as_sdp_when_pr_active = compute_disable_as_sdp_when_pr_active(connector);
>  
>  	if (!intel_dp_is_edp(intel_dp))
>  		return true;
> @@ -1873,7 +1878,7 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
>  								    conn_state);
>  
>  	crtc_state->has_psr = crtc_state->has_panel_replay ? true :
> -		_psr_compute_config(intel_dp, crtc_state);
> +		_psr_compute_config(intel_dp, crtc_state, conn_state);
>  
>  	if (!crtc_state->has_psr)
>  		return;
> @@ -4123,6 +4128,7 @@ psr_source_status(struct intel_dp *intel_dp, struct seq_file *m)
>  }
>  
>  static void intel_psr_sink_capability(struct intel_dp *intel_dp,
> +				      struct intel_connector *connector,
>  				      struct seq_file *m)
>  {
>  	struct intel_psr *psr = &intel_dp->psr;
> @@ -4131,15 +4137,15 @@ static void intel_psr_sink_capability(struct intel_dp *intel_dp,
>  		   str_yes_no(psr->sink_support));
>  
>  	if (psr->sink_support)
> -		seq_printf(m, " [0x%02x]", intel_dp->psr_dpcd[0]);
> -	if (intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_ET_SUPPORTED)
> +		seq_printf(m, " [0x%02x]", connector->dp.psr_dpcd[0]);
> +	if (connector->dp.psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_ET_SUPPORTED)
>  		seq_printf(m, " (Early Transport)");
>  	seq_printf(m, ", Panel Replay = %s", str_yes_no(psr->sink_panel_replay_support));
>  	seq_printf(m, ", Panel Replay Selective Update = %s",
>  		   str_yes_no(psr->sink_panel_replay_su_support));
>  	seq_printf(m, ", Panel Replay DSC support = %s",
>  		   panel_replay_dsc_support_str(psr->sink_panel_replay_dsc_support));
> -	if (intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] &
> +	if (connector->dp.pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] &
>  	    DP_PANEL_REPLAY_EARLY_TRANSPORT_SUPPORT)
>  		seq_printf(m, " (Early Transport)");
>  	seq_printf(m, "\n");
> @@ -4177,7 +4183,8 @@ static void intel_psr_print_mode(struct intel_dp *intel_dp,
>  		seq_printf(m, "  %s\n", psr->no_psr_reason);
>  }
>  
> -static int intel_psr_status(struct seq_file *m, struct intel_dp *intel_dp)
> +static int intel_psr_status(struct seq_file *m, struct intel_dp *intel_dp,
> +			    struct intel_connector *connector)
>  {
>  	struct intel_display *display = to_intel_display(intel_dp);
>  	enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
> @@ -4186,7 +4193,7 @@ static int intel_psr_status(struct seq_file *m, struct intel_dp *intel_dp)
>  	bool enabled;
>  	u32 val, psr2_ctl;
>  
> -	intel_psr_sink_capability(intel_dp, m);
> +	intel_psr_sink_capability(intel_dp, connector, m);
>  
>  	if (!(psr->sink_support || psr->sink_panel_replay_support))
>  		return 0;
> @@ -4302,7 +4309,7 @@ static int i915_edp_psr_status_show(struct seq_file *m, void *data)
>  	if (!intel_dp)
>  		return -ENODEV;
>  
> -	return intel_psr_status(m, intel_dp);
> +	return intel_psr_status(m, intel_dp, intel_dp->attached_connector);
>  }
>  DEFINE_SHOW_ATTRIBUTE(i915_edp_psr_status);
>  
> @@ -4436,7 +4443,7 @@ static int i915_psr_status_show(struct seq_file *m, void *data)
>  	struct intel_connector *connector = m->private;
>  	struct intel_dp *intel_dp = intel_attached_dp(connector);
>  
> -	return intel_psr_status(m, intel_dp);
> +	return intel_psr_status(m, intel_dp, connector);
>  }
>  DEFINE_SHOW_ATTRIBUTE(i915_psr_status);
>  
> -- 
> 2.43.0
> 

[PATCH 5/8] drm/i915/psr: Clear pr_dpcd as well on disconnect

[Jouni Högander]

Currently we are leaving pr_dpcd containing Panel Replay capability DPCD
registers as it is on disconnect. Clear it as well on disconnect.

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 62808cd35f5f2..7195c408d93ab 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -6050,6 +6050,7 @@ intel_dp_detect(struct drm_connector *_connector,
 	if (status == connector_status_disconnected) {
 		intel_dp_test_reset(intel_dp);
 		memset(connector->dp.dsc_dpcd, 0, sizeof(connector->dp.dsc_dpcd));
+		memset(connector->dp.pr_dpcd, 0, sizeof(connector->dp.pr_dpcd));
 		intel_dp->psr.sink_panel_replay_support = false;
 		intel_dp->psr.sink_panel_replay_su_support = false;
 		intel_dp->psr.sink_panel_replay_dsc_support =
-- 
2.43.0

Re: [PATCH 5/8] drm/i915/psr: Clear pr_dpcd as well on disconnect

[Imre Deak]

On Fri, Nov 21, 2025 at 01:16:52PM +0200, Jouni Högander wrote:
> Currently we are leaving pr_dpcd containing Panel Replay capability DPCD
> registers as it is on disconnect. Clear it as well on disconnect.
> 
> Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 62808cd35f5f2..7195c408d93ab 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -6050,6 +6050,7 @@ intel_dp_detect(struct drm_connector *_connector,
>  	if (status == connector_status_disconnected) {
>  		intel_dp_test_reset(intel_dp);
>  		memset(connector->dp.dsc_dpcd, 0, sizeof(connector->dp.dsc_dpcd));
> +		memset(connector->dp.pr_dpcd, 0, sizeof(connector->dp.pr_dpcd));

What about psr_dpcd?

All these resetting of the caps cause a problem if the connector needs
to be modeset after the sink is disconnected (since then the state
computation for the connector will fail seeing these caps being reset).
Instead the caps should be kept intact here, resetting/reiniting them
only when a new sink is connected. Since this is a pre-existing issue,
could you add for now a corrsponding FIXME: comment in this patch?

>  		intel_dp->psr.sink_panel_replay_support = false;
>  		intel_dp->psr.sink_panel_replay_su_support = false;
>  		intel_dp->psr.sink_panel_replay_dsc_support =
> -- 
> 2.43.0
> 

Re: [PATCH 5/8] drm/i915/psr: Clear pr_dpcd as well on disconnect

[Hogander, Jouni]

On Mon, 2025-12-01 at 12:53 +0200, Imre Deak wrote:
> On Fri, Nov 21, 2025 at 01:16:52PM +0200, Jouni Högander wrote:
> > Currently we are leaving pr_dpcd containing Panel Replay capability
> > DPCD
> > registers as it is on disconnect. Clear it as well on disconnect.
> > 
> > Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_dp.c | 1 +
> >  1 file changed, 1 insertion(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > b/drivers/gpu/drm/i915/display/intel_dp.c
> > index 62808cd35f5f2..7195c408d93ab 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -6050,6 +6050,7 @@ intel_dp_detect(struct drm_connector
> > *_connector,
> >  	if (status == connector_status_disconnected) {
> >  		intel_dp_test_reset(intel_dp);
> >  		memset(connector->dp.dsc_dpcd, 0,
> > sizeof(connector->dp.dsc_dpcd));
> > +		memset(connector->dp.pr_dpcd, 0, sizeof(connector-
> > >dp.pr_dpcd));
> 
> What about psr_dpcd?

PSR is only for eDP and can't be disconnected.

> 
> All these resetting of the caps cause a problem if the connector
> needs
> to be modeset after the sink is disconnected (since then the state
> computation for the connector will fail seeing these caps being
> reset).
> Instead the caps should be kept intact here, resetting/reiniting them
> only when a new sink is connected. Since this is a pre-existing
> issue,
> could you add for now a corrsponding FIXME: comment in this patch?

Thank you for pointing this out. I will add the FIXME.

BR,

Jouni Högander

> 
> >  		intel_dp->psr.sink_panel_replay_support = false;
> >  		intel_dp->psr.sink_panel_replay_su_support =
> > false;
> >  		intel_dp->psr.sink_panel_replay_dsc_support =
> > -- 
> > 2.43.0
> > 

Re: [PATCH 5/8] drm/i915/psr: Clear pr_dpcd as well on disconnect

[Imre Deak]

On Mon, Dec 01, 2025 at 01:23:41PM +0200, Jouni Hogander wrote:
> On Mon, 2025-12-01 at 12:53 +0200, Imre Deak wrote:
> > On Fri, Nov 21, 2025 at 01:16:52PM +0200, Jouni Högander wrote:
> > > Currently we are leaving pr_dpcd containing Panel Replay capability
> > > DPCD registers as it is on disconnect. Clear it as well on disconnect.
> > > 
> > > Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/display/intel_dp.c | 1 +
> > >  1 file changed, 1 insertion(+)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > > b/drivers/gpu/drm/i915/display/intel_dp.c
> > > index 62808cd35f5f2..7195c408d93ab 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > > @@ -6050,6 +6050,7 @@ intel_dp_detect(struct drm_connector *_connector,
> > >  	if (status == connector_status_disconnected) {
> > >  		intel_dp_test_reset(intel_dp);
> > >  		memset(connector->dp.dsc_dpcd, 0, sizeof(connector->dp.dsc_dpcd));
> > > +		memset(connector->dp.pr_dpcd, 0, sizeof(connector->dp.pr_dpcd));
> > 
> > What about psr_dpcd?
> 
> PSR is only for eDP and can't be disconnected.

Ok. Panel Replay used on non-eDP has also Selective Update for instance,
but that has separate PR specific capability registers. The same is true
I presume for any other functionality that could be used both on PSR2
and PR.

It's still a bit strange that intel_dp_detect() -> intel_psr_init_dpcd()
-> _psr_init_dpcd() reads psr_dpcd (aka dp.psr_caps.dpcd after your
patch) for non-eDP as well. Even though the values should not be used
anywhere based on the above, I'd still avoid explicitly reading them out
for non-eDP (only as a follow-up imo, no need to change this now).

> > All these resetting of the caps cause a problem if the connector
> > needs to be modeset after the sink is disconnected (since then the
> > state computation for the connector will fail seeing these caps
> > being reset). Instead the caps should be kept intact here,
> > resetting/reiniting them only when a new sink is connected. Since
> > this is a pre-existing issue, could you add for now a corrsponding
> > FIXME: comment in this patch?
> 
> Thank you for pointing this out. I will add the FIXME.
> 
> BR,
> 
> Jouni Högander
> 
> > 
> > >  		intel_dp->psr.sink_panel_replay_support = false;
> > >  		intel_dp->psr.sink_panel_replay_su_support = false;
> > >  		intel_dp->psr.sink_panel_replay_dsc_support =
> > > -- 
> > > 2.43.0

Re: [PATCH 5/8] drm/i915/psr: Clear pr_dpcd as well on disconnect

[Hogander, Jouni]

On Wed, 2025-12-03 at 16:37 +0200, Imre Deak wrote:
> On Mon, Dec 01, 2025 at 01:23:41PM +0200, Jouni Hogander wrote:
> > On Mon, 2025-12-01 at 12:53 +0200, Imre Deak wrote:
> > > On Fri, Nov 21, 2025 at 01:16:52PM +0200, Jouni Högander wrote:
> > > > Currently we are leaving pr_dpcd containing Panel Replay
> > > > capability
> > > > DPCD registers as it is on disconnect. Clear it as well on
> > > > disconnect.
> > > > 
> > > > Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> > > > ---
> > > >  drivers/gpu/drm/i915/display/intel_dp.c | 1 +
> > > >  1 file changed, 1 insertion(+)
> > > > 
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > > > b/drivers/gpu/drm/i915/display/intel_dp.c
> > > > index 62808cd35f5f2..7195c408d93ab 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > > > @@ -6050,6 +6050,7 @@ intel_dp_detect(struct drm_connector
> > > > *_connector,
> > > >  	if (status == connector_status_disconnected) {
> > > >  		intel_dp_test_reset(intel_dp);
> > > >  		memset(connector->dp.dsc_dpcd, 0,
> > > > sizeof(connector->dp.dsc_dpcd));
> > > > +		memset(connector->dp.pr_dpcd, 0,
> > > > sizeof(connector->dp.pr_dpcd));
> > > 
> > > What about psr_dpcd?
> > 
> > PSR is only for eDP and can't be disconnected.
> 
> Ok. Panel Replay used on non-eDP has also Selective Update for
> instance,
> but that has separate PR specific capability registers. The same is
> true
> I presume for any other functionality that could be used both on PSR2
> and PR.
> 
> It's still a bit strange that intel_dp_detect() ->
> intel_psr_init_dpcd()
> -> _psr_init_dpcd() reads psr_dpcd (aka dp.psr_caps.dpcd after your
> patch) for non-eDP as well. Even though the values should not be used
> anywhere based on the above, I'd still avoid explicitly reading them
> out
> for non-eDP (only as a follow-up imo, no need to change this now).

Ok, I will take care of that.

Another thing I have been recently wondering is the eDP/DP version.
Generally speaking: should I check eDP/DP version before checking the
feature of some specific version. I have now seen couple of cases where
panel is stating Panel Replay support, but still saying it's eDP
version 1.4. and Panel Replay is non-functional.(Related patch in
trybot: https://patchwork.freedesktop.org/series/157760/)

BR,

Jouni Högander

> 
> > > All these resetting of the caps cause a problem if the connector
> > > needs to be modeset after the sink is disconnected (since then
> > > the
> > > state computation for the connector will fail seeing these caps
> > > being reset). Instead the caps should be kept intact here,
> > > resetting/reiniting them only when a new sink is connected. Since
> > > this is a pre-existing issue, could you add for now a
> > > corrsponding
> > > FIXME: comment in this patch?
> > 
> > Thank you for pointing this out. I will add the FIXME.
> > 
> > BR,
> > 
> > Jouni Högander
> > 
> > > 
> > > >  		intel_dp->psr.sink_panel_replay_support =
> > > > false;
> > > >  		intel_dp->psr.sink_panel_replay_su_support =
> > > > false;
> > > >  		intel_dp->psr.sink_panel_replay_dsc_support =
> > > > -- 
> > > > 2.43.0

[PATCH 6/8] drm/i915/psr: Move Panel Replay DSC sink support data to intel_connector

[Jouni Högander]

As a preparation for MST Panel Replay we need to move Panel Replay sink
related data into intel_connector. Move Panel Replay DSC sink support data
as well into intel_connector.

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
---
 .../gpu/drm/i915/display/intel_display_types.h    | 15 ++++++++-------
 drivers/gpu/drm/i915/display/intel_dp.c           |  2 +-
 drivers/gpu/drm/i915/display/intel_psr.c          | 13 +++++++------
 3 files changed, 16 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 8587d2c527f72..e1d47496ea4de 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -509,6 +509,12 @@ struct intel_hdcp {
 	bool force_hdcp14;
 };
 
+enum intel_panel_replay_dsc_support {
+	INTEL_DP_PANEL_REPLAY_DSC_NOT_SUPPORTED,
+	INTEL_DP_PANEL_REPLAY_DSC_FULL_FRAME_ONLY,
+	INTEL_DP_PANEL_REPLAY_DSC_SELECTIVE_UPDATE,
+};
+
 struct intel_connector {
 	struct drm_connector base;
 	/*
@@ -566,6 +572,8 @@ struct intel_connector {
 		} dsc_branch_caps;
 
 		struct {
+			enum intel_panel_replay_dsc_support dsc_support;
+
 			u16 su_w_granularity;
 			u16 su_y_granularity;
 		} panel_replay_caps;
@@ -967,12 +975,6 @@ struct intel_csc_matrix {
 	u16 postoff[3];
 };
 
-enum intel_panel_replay_dsc_support {
-	INTEL_DP_PANEL_REPLAY_DSC_NOT_SUPPORTED,
-	INTEL_DP_PANEL_REPLAY_DSC_FULL_FRAME_ONLY,
-	INTEL_DP_PANEL_REPLAY_DSC_SELECTIVE_UPDATE,
-};
-
 struct scaler_filter_coeff {
 	u16 sign;
 	u16 exp;
@@ -1744,7 +1746,6 @@ struct intel_psr {
 	bool source_panel_replay_support;
 	bool sink_panel_replay_support;
 	bool sink_panel_replay_su_support;
-	enum intel_panel_replay_dsc_support sink_panel_replay_dsc_support;
 	bool panel_replay_enabled;
 	u32 dc3co_exitline;
 	u32 dc3co_exit_delay;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 7195c408d93ab..d32f476c288c1 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -6053,7 +6053,7 @@ intel_dp_detect(struct drm_connector *_connector,
 		memset(connector->dp.pr_dpcd, 0, sizeof(connector->dp.pr_dpcd));
 		intel_dp->psr.sink_panel_replay_support = false;
 		intel_dp->psr.sink_panel_replay_su_support = false;
-		intel_dp->psr.sink_panel_replay_dsc_support =
+		connector->dp.panel_replay_caps.dsc_support =
 			INTEL_DP_PANEL_REPLAY_DSC_NOT_SUPPORTED;
 
 		intel_dp_mst_disconnect(intel_dp);
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index b488be8c917dc..4bae39f745ea0 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -644,13 +644,13 @@ static void _panel_replay_init_dpcd(struct intel_dp *intel_dp, struct intel_conn
 		_panel_replay_compute_su_granularity(intel_dp, connector);
 	}
 
-	intel_dp->psr.sink_panel_replay_dsc_support = compute_pr_dsc_support(connector);
+	connector->dp.panel_replay_caps.dsc_support = compute_pr_dsc_support(connector);
 
 	drm_dbg_kms(display->drm,
 		    "Panel replay %sis supported by panel (in DSC mode: %s)\n",
 		    intel_dp->psr.sink_panel_replay_su_support ?
 		    "selective_update " : "",
-		    panel_replay_dsc_support_str(intel_dp->psr.sink_panel_replay_dsc_support));
+		    panel_replay_dsc_support_str(connector->dp.panel_replay_caps.dsc_support));
 }
 
 static void _psr_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector)
@@ -1659,7 +1659,7 @@ static bool intel_sel_update_config_valid(struct intel_dp *intel_dp,
 			goto unsupported;
 
 		if (intel_dsc_enabled_on_link(crtc_state) &&
-		    intel_dp->psr.sink_panel_replay_dsc_support !=
+		    connector->dp.panel_replay_caps.dsc_support !=
 		    INTEL_DP_PANEL_REPLAY_DSC_SELECTIVE_UPDATE) {
 			drm_dbg_kms(display->drm,
 				    "Selective update with Panel Replay not enabled because it's not supported with DSC\n");
@@ -1756,7 +1756,7 @@ static bool _panel_replay_compute_config(struct intel_dp *intel_dp,
 	}
 
 	if (intel_dsc_enabled_on_link(crtc_state) &&
-	    intel_dp->psr.sink_panel_replay_dsc_support ==
+	    connector->dp.panel_replay_caps.dsc_support ==
 	    INTEL_DP_PANEL_REPLAY_DSC_NOT_SUPPORTED) {
 		drm_dbg_kms(display->drm,
 			    "Panel Replay not enabled because it's not supported with DSC\n");
@@ -1841,6 +1841,7 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
 			      struct drm_connector_state *conn_state)
 {
 	struct intel_display *display = to_intel_display(intel_dp);
+	struct intel_connector *connector = to_intel_connector(conn_state->connector);
 	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
 
 	if (!psr_global_enabled(intel_dp)) {
@@ -1872,7 +1873,7 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
 	}
 
 	/* Only used for state verification. */
-	crtc_state->panel_replay_dsc_support = intel_dp->psr.sink_panel_replay_dsc_support;
+	crtc_state->panel_replay_dsc_support = connector->dp.panel_replay_caps.dsc_support;
 	crtc_state->has_panel_replay = _panel_replay_compute_config(intel_dp,
 								    crtc_state,
 								    conn_state);
@@ -4144,7 +4145,7 @@ static void intel_psr_sink_capability(struct intel_dp *intel_dp,
 	seq_printf(m, ", Panel Replay Selective Update = %s",
 		   str_yes_no(psr->sink_panel_replay_su_support));
 	seq_printf(m, ", Panel Replay DSC support = %s",
-		   panel_replay_dsc_support_str(psr->sink_panel_replay_dsc_support));
+		   panel_replay_dsc_support_str(connector->dp.panel_replay_caps.dsc_support));
 	if (connector->dp.pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] &
 	    DP_PANEL_REPLAY_EARLY_TRANSPORT_SUPPORT)
 		seq_printf(m, " (Early Transport)");
-- 
2.43.0

Re: [PATCH 6/8] drm/i915/psr: Move Panel Replay DSC sink support data to intel_connector

[Imre Deak]

On Fri, Nov 21, 2025 at 01:16:53PM +0200, Jouni Högander wrote:
> As a preparation for MST Panel Replay we need to move Panel Replay sink
> related data into intel_connector. Move Panel Replay DSC sink support data
> as well into intel_connector.
> 
> Signed-off-by: Jouni Högander <jouni.hogander@intel.com>

Reviewed-by: Imre Deak <imre.deak@intel.com>

> ---
>  .../gpu/drm/i915/display/intel_display_types.h    | 15 ++++++++-------
>  drivers/gpu/drm/i915/display/intel_dp.c           |  2 +-
>  drivers/gpu/drm/i915/display/intel_psr.c          | 13 +++++++------
>  3 files changed, 16 insertions(+), 14 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 8587d2c527f72..e1d47496ea4de 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -509,6 +509,12 @@ struct intel_hdcp {
>  	bool force_hdcp14;
>  };
>  
> +enum intel_panel_replay_dsc_support {
> +	INTEL_DP_PANEL_REPLAY_DSC_NOT_SUPPORTED,
> +	INTEL_DP_PANEL_REPLAY_DSC_FULL_FRAME_ONLY,
> +	INTEL_DP_PANEL_REPLAY_DSC_SELECTIVE_UPDATE,
> +};
> +
>  struct intel_connector {
>  	struct drm_connector base;
>  	/*
> @@ -566,6 +572,8 @@ struct intel_connector {
>  		} dsc_branch_caps;
>  
>  		struct {
> +			enum intel_panel_replay_dsc_support dsc_support;
> +
>  			u16 su_w_granularity;
>  			u16 su_y_granularity;
>  		} panel_replay_caps;
> @@ -967,12 +975,6 @@ struct intel_csc_matrix {
>  	u16 postoff[3];
>  };
>  
> -enum intel_panel_replay_dsc_support {
> -	INTEL_DP_PANEL_REPLAY_DSC_NOT_SUPPORTED,
> -	INTEL_DP_PANEL_REPLAY_DSC_FULL_FRAME_ONLY,
> -	INTEL_DP_PANEL_REPLAY_DSC_SELECTIVE_UPDATE,
> -};
> -
>  struct scaler_filter_coeff {
>  	u16 sign;
>  	u16 exp;
> @@ -1744,7 +1746,6 @@ struct intel_psr {
>  	bool source_panel_replay_support;
>  	bool sink_panel_replay_support;
>  	bool sink_panel_replay_su_support;
> -	enum intel_panel_replay_dsc_support sink_panel_replay_dsc_support;
>  	bool panel_replay_enabled;
>  	u32 dc3co_exitline;
>  	u32 dc3co_exit_delay;
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 7195c408d93ab..d32f476c288c1 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -6053,7 +6053,7 @@ intel_dp_detect(struct drm_connector *_connector,
>  		memset(connector->dp.pr_dpcd, 0, sizeof(connector->dp.pr_dpcd));
>  		intel_dp->psr.sink_panel_replay_support = false;
>  		intel_dp->psr.sink_panel_replay_su_support = false;
> -		intel_dp->psr.sink_panel_replay_dsc_support =
> +		connector->dp.panel_replay_caps.dsc_support =
>  			INTEL_DP_PANEL_REPLAY_DSC_NOT_SUPPORTED;
>  
>  		intel_dp_mst_disconnect(intel_dp);
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index b488be8c917dc..4bae39f745ea0 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -644,13 +644,13 @@ static void _panel_replay_init_dpcd(struct intel_dp *intel_dp, struct intel_conn
>  		_panel_replay_compute_su_granularity(intel_dp, connector);
>  	}
>  
> -	intel_dp->psr.sink_panel_replay_dsc_support = compute_pr_dsc_support(connector);
> +	connector->dp.panel_replay_caps.dsc_support = compute_pr_dsc_support(connector);
>  
>  	drm_dbg_kms(display->drm,
>  		    "Panel replay %sis supported by panel (in DSC mode: %s)\n",
>  		    intel_dp->psr.sink_panel_replay_su_support ?
>  		    "selective_update " : "",
> -		    panel_replay_dsc_support_str(intel_dp->psr.sink_panel_replay_dsc_support));
> +		    panel_replay_dsc_support_str(connector->dp.panel_replay_caps.dsc_support));
>  }
>  
>  static void _psr_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector)
> @@ -1659,7 +1659,7 @@ static bool intel_sel_update_config_valid(struct intel_dp *intel_dp,
>  			goto unsupported;
>  
>  		if (intel_dsc_enabled_on_link(crtc_state) &&
> -		    intel_dp->psr.sink_panel_replay_dsc_support !=
> +		    connector->dp.panel_replay_caps.dsc_support !=
>  		    INTEL_DP_PANEL_REPLAY_DSC_SELECTIVE_UPDATE) {
>  			drm_dbg_kms(display->drm,
>  				    "Selective update with Panel Replay not enabled because it's not supported with DSC\n");
> @@ -1756,7 +1756,7 @@ static bool _panel_replay_compute_config(struct intel_dp *intel_dp,
>  	}
>  
>  	if (intel_dsc_enabled_on_link(crtc_state) &&
> -	    intel_dp->psr.sink_panel_replay_dsc_support ==
> +	    connector->dp.panel_replay_caps.dsc_support ==
>  	    INTEL_DP_PANEL_REPLAY_DSC_NOT_SUPPORTED) {
>  		drm_dbg_kms(display->drm,
>  			    "Panel Replay not enabled because it's not supported with DSC\n");
> @@ -1841,6 +1841,7 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
>  			      struct drm_connector_state *conn_state)
>  {
>  	struct intel_display *display = to_intel_display(intel_dp);
> +	struct intel_connector *connector = to_intel_connector(conn_state->connector);
>  	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
>  
>  	if (!psr_global_enabled(intel_dp)) {
> @@ -1872,7 +1873,7 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
>  	}
>  
>  	/* Only used for state verification. */
> -	crtc_state->panel_replay_dsc_support = intel_dp->psr.sink_panel_replay_dsc_support;
> +	crtc_state->panel_replay_dsc_support = connector->dp.panel_replay_caps.dsc_support;
>  	crtc_state->has_panel_replay = _panel_replay_compute_config(intel_dp,
>  								    crtc_state,
>  								    conn_state);
> @@ -4144,7 +4145,7 @@ static void intel_psr_sink_capability(struct intel_dp *intel_dp,
>  	seq_printf(m, ", Panel Replay Selective Update = %s",
>  		   str_yes_no(psr->sink_panel_replay_su_support));
>  	seq_printf(m, ", Panel Replay DSC support = %s",
> -		   panel_replay_dsc_support_str(psr->sink_panel_replay_dsc_support));
> +		   panel_replay_dsc_support_str(connector->dp.panel_replay_caps.dsc_support));
>  	if (connector->dp.pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] &
>  	    DP_PANEL_REPLAY_EARLY_TRANSPORT_SUPPORT)
>  		seq_printf(m, " (Early Transport)");
> -- 
> 2.43.0
> 

[PATCH 7/8] drm/i915/psr: Move sink PSR and Panel Replay booleans to intel_connector

[Jouni Högander]

As a preparation for MST Panel Replay we need to move Panel Replay sink
related data into intel_connector. Move sink support booleans as well
into intel_connector. Generally this is more correct place for this data so
move PSR versions as well.

Still sink_support and sink_panel_replay_support are kept to keep CAN_PSR
and CAN_PANEL_REPLAY macros.

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
---
 .../drm/i915/display/intel_display_types.h    |  7 ++-
 drivers/gpu/drm/i915/display/intel_dp.c       |  4 +-
 drivers/gpu/drm/i915/display/intel_psr.c      | 44 +++++++++++--------
 3 files changed, 33 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index e1d47496ea4de..04d21333130f9 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -572,6 +572,8 @@ struct intel_connector {
 		} dsc_branch_caps;
 
 		struct {
+			bool support;
+			bool su_support;
 			enum intel_panel_replay_dsc_support dsc_support;
 
 			u16 su_w_granularity;
@@ -579,6 +581,9 @@ struct intel_connector {
 		} panel_replay_caps;
 
 		struct {
+			bool support;
+			bool su_support;
+
 			u16 su_w_granularity;
 			u16 su_y_granularity;
 		} psr_caps;
@@ -1729,7 +1734,6 @@ struct intel_psr {
 	bool active;
 	struct work_struct work;
 	unsigned int busy_frontbuffer_bits;
-	bool sink_psr2_support;
 	bool link_standby;
 	bool sel_update_enabled;
 	bool psr2_sel_fetch_enabled;
@@ -1745,7 +1749,6 @@ struct intel_psr {
 	u16 su_y_granularity;
 	bool source_panel_replay_support;
 	bool sink_panel_replay_support;
-	bool sink_panel_replay_su_support;
 	bool panel_replay_enabled;
 	u32 dc3co_exitline;
 	u32 dc3co_exit_delay;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index d32f476c288c1..2452302937c73 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -6052,10 +6052,12 @@ intel_dp_detect(struct drm_connector *_connector,
 		memset(connector->dp.dsc_dpcd, 0, sizeof(connector->dp.dsc_dpcd));
 		memset(connector->dp.pr_dpcd, 0, sizeof(connector->dp.pr_dpcd));
 		intel_dp->psr.sink_panel_replay_support = false;
-		intel_dp->psr.sink_panel_replay_su_support = false;
+		connector->dp.panel_replay_caps.support = false;
+		connector->dp.panel_replay_caps.su_support = false;
 		connector->dp.panel_replay_caps.dsc_support =
 			INTEL_DP_PANEL_REPLAY_DSC_NOT_SUPPORTED;
 
+
 		intel_dp_mst_disconnect(intel_dp);
 
 		intel_dp_tunnel_disconnect(intel_dp);
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 4bae39f745ea0..e6268d692f89d 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -635,11 +635,12 @@ static void _panel_replay_init_dpcd(struct intel_dp *intel_dp, struct intel_conn
 		}
 	}
 
+	connector->dp.panel_replay_caps.support = true;
 	intel_dp->psr.sink_panel_replay_support = true;
 
 	if (connector->dp.pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] &
 	    DP_PANEL_REPLAY_SU_SUPPORT) {
-		intel_dp->psr.sink_panel_replay_su_support = true;
+		connector->dp.panel_replay_caps.su_support = true;
 
 		_panel_replay_compute_su_granularity(intel_dp, connector);
 	}
@@ -648,7 +649,7 @@ static void _panel_replay_init_dpcd(struct intel_dp *intel_dp, struct intel_conn
 
 	drm_dbg_kms(display->drm,
 		    "Panel replay %sis supported by panel (in DSC mode: %s)\n",
-		    intel_dp->psr.sink_panel_replay_su_support ?
+		    connector->dp.panel_replay_caps.su_support ?
 		    "selective_update " : "",
 		    panel_replay_dsc_support_str(connector->dp.panel_replay_caps.dsc_support));
 }
@@ -681,7 +682,9 @@ static void _psr_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *co
 		return;
 	}
 
+	connector->dp.psr_caps.support = true;
 	intel_dp->psr.sink_support = true;
+
 	intel_dp->psr.sink_sync_latency =
 		intel_dp_get_sink_sync_latency(intel_dp);
 
@@ -701,13 +704,13 @@ static void _psr_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *co
 		 * Y-coordinate requirement panels we would need to enable
 		 * GTC first.
 		 */
-		intel_dp->psr.sink_psr2_support = y_req &&
+		connector->dp.psr_caps.su_support = y_req &&
 			intel_alpm_aux_wake_supported(intel_dp);
 		drm_dbg_kms(display->drm, "PSR2 %ssupported\n",
-			    intel_dp->psr.sink_psr2_support ? "" : "not ");
+			    connector->dp.psr_caps.su_support ? "" : "not ");
 	}
 
-	if (intel_dp->psr.sink_psr2_support)
+	if (connector->dp.psr_caps.su_support)
 		_psr_compute_su_granularity(intel_dp, connector);
 }
 
@@ -1522,14 +1525,16 @@ static bool alpm_config_valid(struct intel_dp *intel_dp,
 }
 
 static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
-				    struct intel_crtc_state *crtc_state)
+				    struct intel_crtc_state *crtc_state,
+				    struct drm_connector_state *conn_state)
 {
 	struct intel_display *display = to_intel_display(intel_dp);
+	struct intel_connector *connector = to_intel_connector(conn_state->connector);
 	int crtc_hdisplay = crtc_state->hw.adjusted_mode.crtc_hdisplay;
 	int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay;
 	int psr_max_h = 0, psr_max_v = 0, max_bpp = 0;
 
-	if (!intel_dp->psr.sink_psr2_support || display->params.enable_psr == 1)
+	if (!connector->dp.psr_caps.su_support || display->params.enable_psr == 1)
 		return false;
 
 	/* JSL and EHL only supports eDP 1.3 */
@@ -1642,7 +1647,8 @@ static bool intel_sel_update_config_valid(struct intel_dp *intel_dp,
 		goto unsupported;
 	}
 
-	if (!crtc_state->has_panel_replay && !intel_psr2_config_valid(intel_dp, crtc_state))
+	if (!crtc_state->has_panel_replay && !intel_psr2_config_valid(intel_dp, crtc_state,
+								      conn_state))
 		goto unsupported;
 
 	if (!_compute_psr2_sdp_prior_scanline_indication(intel_dp, crtc_state)) {
@@ -1655,7 +1661,7 @@ static bool intel_sel_update_config_valid(struct intel_dp *intel_dp,
 		if (DISPLAY_VER(display) < 14)
 			goto unsupported;
 
-		if (!intel_dp->psr.sink_panel_replay_su_support)
+		if (!connector->dp.panel_replay_caps.su_support)
 			goto unsupported;
 
 		if (intel_dsc_enabled_on_link(crtc_state) &&
@@ -1744,6 +1750,9 @@ static bool _panel_replay_compute_config(struct intel_dp *intel_dp,
 	if (!CAN_PANEL_REPLAY(intel_dp))
 		return false;
 
+	if (!connector->dp.panel_replay_caps.support)
+		return false;
+
 	if (!panel_replay_global_enabled(intel_dp)) {
 		drm_dbg_kms(display->drm, "Panel Replay disabled by flag\n");
 		return false;
@@ -4128,22 +4137,19 @@ psr_source_status(struct intel_dp *intel_dp, struct seq_file *m)
 	seq_printf(m, "Source PSR/PanelReplay status: %s [0x%08x]\n", status, val);
 }
 
-static void intel_psr_sink_capability(struct intel_dp *intel_dp,
-				      struct intel_connector *connector,
+static void intel_psr_sink_capability(struct intel_connector *connector,
 				      struct seq_file *m)
 {
-	struct intel_psr *psr = &intel_dp->psr;
-
 	seq_printf(m, "Sink support: PSR = %s",
-		   str_yes_no(psr->sink_support));
+		   str_yes_no(connector->dp.psr_caps.support));
 
-	if (psr->sink_support)
+	if (connector->dp.psr_caps.support)
 		seq_printf(m, " [0x%02x]", connector->dp.psr_dpcd[0]);
 	if (connector->dp.psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_ET_SUPPORTED)
 		seq_printf(m, " (Early Transport)");
-	seq_printf(m, ", Panel Replay = %s", str_yes_no(psr->sink_panel_replay_support));
+	seq_printf(m, ", Panel Replay = %s", str_yes_no(connector->dp.panel_replay_caps.support));
 	seq_printf(m, ", Panel Replay Selective Update = %s",
-		   str_yes_no(psr->sink_panel_replay_su_support));
+		   str_yes_no(connector->dp.panel_replay_caps.su_support));
 	seq_printf(m, ", Panel Replay DSC support = %s",
 		   panel_replay_dsc_support_str(connector->dp.panel_replay_caps.dsc_support));
 	if (connector->dp.pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] &
@@ -4194,9 +4200,9 @@ static int intel_psr_status(struct seq_file *m, struct intel_dp *intel_dp,
 	bool enabled;
 	u32 val, psr2_ctl;
 
-	intel_psr_sink_capability(intel_dp, connector, m);
+	intel_psr_sink_capability(connector, m);
 
-	if (!(psr->sink_support || psr->sink_panel_replay_support))
+	if (!(connector->dp.psr_caps.support || connector->dp.panel_replay_caps.support))
 		return 0;
 
 	wakeref = intel_display_rpm_get(display);
-- 
2.43.0

Re: [PATCH 7/8] drm/i915/psr: Move sink PSR and Panel Replay booleans to intel_connector

[Imre Deak]

On Fri, Nov 21, 2025 at 01:16:54PM +0200, Jouni Högander wrote:
> As a preparation for MST Panel Replay we need to move Panel Replay sink
> related data into intel_connector. Move sink support booleans as well
> into intel_connector. Generally this is more correct place for this data so
> move PSR versions as well.
> 
> Still sink_support and sink_panel_replay_support are kept to keep CAN_PSR
> and CAN_PANEL_REPLAY macros.

Would be good to mention what's the plan with these macros (they'll take
a connector instead of an intel_dp pointer?)

> 
> Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> ---
>  .../drm/i915/display/intel_display_types.h    |  7 ++-
>  drivers/gpu/drm/i915/display/intel_dp.c       |  4 +-
>  drivers/gpu/drm/i915/display/intel_psr.c      | 44 +++++++++++--------
>  3 files changed, 33 insertions(+), 22 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index e1d47496ea4de..04d21333130f9 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -572,6 +572,8 @@ struct intel_connector {
>  		} dsc_branch_caps;
>  
>  		struct {
> +			bool support;
> +			bool su_support;
>  			enum intel_panel_replay_dsc_support dsc_support;
>  
>  			u16 su_w_granularity;
> @@ -579,6 +581,9 @@ struct intel_connector {
>  		} panel_replay_caps;
>  
>  		struct {
> +			bool support;
> +			bool su_support;
> +
>  			u16 su_w_granularity;
>  			u16 su_y_granularity;
>  		} psr_caps;
> @@ -1729,7 +1734,6 @@ struct intel_psr {
>  	bool active;
>  	struct work_struct work;
>  	unsigned int busy_frontbuffer_bits;
> -	bool sink_psr2_support;
>  	bool link_standby;
>  	bool sel_update_enabled;
>  	bool psr2_sel_fetch_enabled;
> @@ -1745,7 +1749,6 @@ struct intel_psr {
>  	u16 su_y_granularity;
>  	bool source_panel_replay_support;
>  	bool sink_panel_replay_support;
> -	bool sink_panel_replay_su_support;
>  	bool panel_replay_enabled;
>  	u32 dc3co_exitline;
>  	u32 dc3co_exit_delay;
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index d32f476c288c1..2452302937c73 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -6052,10 +6052,12 @@ intel_dp_detect(struct drm_connector *_connector,
>  		memset(connector->dp.dsc_dpcd, 0, sizeof(connector->dp.dsc_dpcd));
>  		memset(connector->dp.pr_dpcd, 0, sizeof(connector->dp.pr_dpcd));
>  		intel_dp->psr.sink_panel_replay_support = false;
> -		intel_dp->psr.sink_panel_replay_su_support = false;
> +		connector->dp.panel_replay_caps.support = false;
> +		connector->dp.panel_replay_caps.su_support = false;

What about resetting PSR counterparts?

>  		connector->dp.panel_replay_caps.dsc_support =
>  			INTEL_DP_PANEL_REPLAY_DSC_NOT_SUPPORTED;
>  
> +

Extra w/s.

>  		intel_dp_mst_disconnect(intel_dp);
>  
>  		intel_dp_tunnel_disconnect(intel_dp);
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 4bae39f745ea0..e6268d692f89d 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -635,11 +635,12 @@ static void _panel_replay_init_dpcd(struct intel_dp *intel_dp, struct intel_conn
>  		}
>  	}
>  
> +	connector->dp.panel_replay_caps.support = true;
>  	intel_dp->psr.sink_panel_replay_support = true;
>  
>  	if (connector->dp.pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] &
>  	    DP_PANEL_REPLAY_SU_SUPPORT) {
> -		intel_dp->psr.sink_panel_replay_su_support = true;
> +		connector->dp.panel_replay_caps.su_support = true;
>  
>  		_panel_replay_compute_su_granularity(intel_dp, connector);
>  	}
> @@ -648,7 +649,7 @@ static void _panel_replay_init_dpcd(struct intel_dp *intel_dp, struct intel_conn
>  
>  	drm_dbg_kms(display->drm,
>  		    "Panel replay %sis supported by panel (in DSC mode: %s)\n",
> -		    intel_dp->psr.sink_panel_replay_su_support ?
> +		    connector->dp.panel_replay_caps.su_support ?
>  		    "selective_update " : "",
>  		    panel_replay_dsc_support_str(connector->dp.panel_replay_caps.dsc_support));
>  }
> @@ -681,7 +682,9 @@ static void _psr_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *co
>  		return;
>  	}
>  
> +	connector->dp.psr_caps.support = true;
>  	intel_dp->psr.sink_support = true;
> +
>  	intel_dp->psr.sink_sync_latency =
>  		intel_dp_get_sink_sync_latency(intel_dp);
>  
> @@ -701,13 +704,13 @@ static void _psr_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *co
>  		 * Y-coordinate requirement panels we would need to enable
>  		 * GTC first.
>  		 */
> -		intel_dp->psr.sink_psr2_support = y_req &&
> +		connector->dp.psr_caps.su_support = y_req &&
>  			intel_alpm_aux_wake_supported(intel_dp);
>  		drm_dbg_kms(display->drm, "PSR2 %ssupported\n",
> -			    intel_dp->psr.sink_psr2_support ? "" : "not ");
> +			    connector->dp.psr_caps.su_support ? "" : "not ");
>  	}
>  
> -	if (intel_dp->psr.sink_psr2_support)
> +	if (connector->dp.psr_caps.su_support)
>  		_psr_compute_su_granularity(intel_dp, connector);
>  }
>  
> @@ -1522,14 +1525,16 @@ static bool alpm_config_valid(struct intel_dp *intel_dp,
>  }
>  
>  static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
> -				    struct intel_crtc_state *crtc_state)
> +				    struct intel_crtc_state *crtc_state,
> +				    struct drm_connector_state *conn_state)
>  {
>  	struct intel_display *display = to_intel_display(intel_dp);
> +	struct intel_connector *connector = to_intel_connector(conn_state->connector);
>  	int crtc_hdisplay = crtc_state->hw.adjusted_mode.crtc_hdisplay;
>  	int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay;
>  	int psr_max_h = 0, psr_max_v = 0, max_bpp = 0;
>  
> -	if (!intel_dp->psr.sink_psr2_support || display->params.enable_psr == 1)
> +	if (!connector->dp.psr_caps.su_support || display->params.enable_psr == 1)
>  		return false;
>  
>  	/* JSL and EHL only supports eDP 1.3 */
> @@ -1642,7 +1647,8 @@ static bool intel_sel_update_config_valid(struct intel_dp *intel_dp,
>  		goto unsupported;
>  	}
>  
> -	if (!crtc_state->has_panel_replay && !intel_psr2_config_valid(intel_dp, crtc_state))
> +	if (!crtc_state->has_panel_replay && !intel_psr2_config_valid(intel_dp, crtc_state,
> +								      conn_state))
>  		goto unsupported;
>  
>  	if (!_compute_psr2_sdp_prior_scanline_indication(intel_dp, crtc_state)) {
> @@ -1655,7 +1661,7 @@ static bool intel_sel_update_config_valid(struct intel_dp *intel_dp,
>  		if (DISPLAY_VER(display) < 14)
>  			goto unsupported;
>  
> -		if (!intel_dp->psr.sink_panel_replay_su_support)
> +		if (!connector->dp.panel_replay_caps.su_support)
>  			goto unsupported;
>  
>  		if (intel_dsc_enabled_on_link(crtc_state) &&
> @@ -1744,6 +1750,9 @@ static bool _panel_replay_compute_config(struct intel_dp *intel_dp,
>  	if (!CAN_PANEL_REPLAY(intel_dp))
>  		return false;
>  
> +	if (!connector->dp.panel_replay_caps.support)
> +		return false;
> +
>  	if (!panel_replay_global_enabled(intel_dp)) {
>  		drm_dbg_kms(display->drm, "Panel Replay disabled by flag\n");
>  		return false;
> @@ -4128,22 +4137,19 @@ psr_source_status(struct intel_dp *intel_dp, struct seq_file *m)
>  	seq_printf(m, "Source PSR/PanelReplay status: %s [0x%08x]\n", status, val);
>  }
>  
> -static void intel_psr_sink_capability(struct intel_dp *intel_dp,
> -				      struct intel_connector *connector,
> +static void intel_psr_sink_capability(struct intel_connector *connector,
>  				      struct seq_file *m)
>  {
> -	struct intel_psr *psr = &intel_dp->psr;
> -
>  	seq_printf(m, "Sink support: PSR = %s",
> -		   str_yes_no(psr->sink_support));
> +		   str_yes_no(connector->dp.psr_caps.support));
>  
> -	if (psr->sink_support)
> +	if (connector->dp.psr_caps.support)
>  		seq_printf(m, " [0x%02x]", connector->dp.psr_dpcd[0]);
>  	if (connector->dp.psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_ET_SUPPORTED)
>  		seq_printf(m, " (Early Transport)");
> -	seq_printf(m, ", Panel Replay = %s", str_yes_no(psr->sink_panel_replay_support));
> +	seq_printf(m, ", Panel Replay = %s", str_yes_no(connector->dp.panel_replay_caps.support));
>  	seq_printf(m, ", Panel Replay Selective Update = %s",
> -		   str_yes_no(psr->sink_panel_replay_su_support));
> +		   str_yes_no(connector->dp.panel_replay_caps.su_support));
>  	seq_printf(m, ", Panel Replay DSC support = %s",
>  		   panel_replay_dsc_support_str(connector->dp.panel_replay_caps.dsc_support));
>  	if (connector->dp.pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] &
> @@ -4194,9 +4200,9 @@ static int intel_psr_status(struct seq_file *m, struct intel_dp *intel_dp,
>  	bool enabled;
>  	u32 val, psr2_ctl;
>  
> -	intel_psr_sink_capability(intel_dp, connector, m);
> +	intel_psr_sink_capability(connector, m);
>  
> -	if (!(psr->sink_support || psr->sink_panel_replay_support))
> +	if (!(connector->dp.psr_caps.support || connector->dp.panel_replay_caps.support))
>  		return 0;
>  
>  	wakeref = intel_display_rpm_get(display);
> -- 
> 2.43.0
> 

[PATCH 8/8] drm/i915/psr: Move sink_sync_latency to intel_connector

[Jouni Högander]

As everything else related to PSR and Panel Replay capabilities are moved
into intel_connector move sink_sync_latency as well.

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_types.h | 3 ++-
 drivers/gpu/drm/i915/display/intel_psr.c           | 8 ++++----
 2 files changed, 6 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 04d21333130f9..77e1948aef2ff 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -586,6 +586,8 @@ struct intel_connector {
 
 			u16 su_w_granularity;
 			u16 su_y_granularity;
+
+			u8 sync_latency;
 		} psr_caps;
 	} dp;
 
@@ -1740,7 +1742,6 @@ struct intel_psr {
 	bool psr2_sel_fetch_cff_enabled;
 	bool su_region_et_enabled;
 	bool req_psr2_sdp_prior_scanline;
-	u8 sink_sync_latency;
 	ktime_t last_entry_attempt;
 	ktime_t last_exit;
 	bool sink_not_reliable;
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index e6268d692f89d..bbd1b0e8beecb 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -685,8 +685,7 @@ static void _psr_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *co
 	connector->dp.psr_caps.support = true;
 	intel_dp->psr.sink_support = true;
 
-	intel_dp->psr.sink_sync_latency =
-		intel_dp_get_sink_sync_latency(intel_dp);
+	connector->dp.psr_caps.sync_latency = intel_dp_get_sink_sync_latency(intel_dp);
 
 	if (DISPLAY_VER(display) >= 9 &&
 	    connector->dp.psr_dpcd[0] >= DP_PSR2_WITH_Y_COORD_IS_SUPPORTED) {
@@ -911,7 +910,7 @@ static u8 psr_compute_idle_frames(struct intel_dp *intel_dp)
 	 * off-by-one issue that HW has in some cases.
 	 */
 	idle_frames = max(6, connector->panel.vbt.psr.idle_frames);
-	idle_frames = max(idle_frames, intel_dp->psr.sink_sync_latency + 1);
+	idle_frames = max(idle_frames, connector->dp.psr_caps.sync_latency + 1);
 
 	if (drm_WARN_ON(display->drm, idle_frames > 0xf))
 		idle_frames = 0xf;
@@ -1006,10 +1005,11 @@ static int psr2_block_count(struct intel_dp *intel_dp)
 
 static u8 frames_before_su_entry(struct intel_dp *intel_dp)
 {
+	struct intel_connector *connector = intel_dp->attached_connector;
 	u8 frames_before_su_entry;
 
 	frames_before_su_entry = max_t(u8,
-				       intel_dp->psr.sink_sync_latency + 1,
+				       connector->dp.psr_caps.sync_latency + 1,
 				       2);
 
 	/* Entry setup frames must be at least 1 less than frames before SU entry */
-- 
2.43.0

Re: [PATCH 8/8] drm/i915/psr: Move sink_sync_latency to intel_connector

[Imre Deak]

On Fri, Nov 21, 2025 at 01:16:55PM +0200, Jouni Högander wrote:
> As everything else related to PSR and Panel Replay capabilities are moved
> into intel_connector move sink_sync_latency as well.
> 
> Signed-off-by: Jouni Högander <jouni.hogander@intel.com>

Reviewed-by: Imre Deak <imre.deak@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_display_types.h | 3 ++-
>  drivers/gpu/drm/i915/display/intel_psr.c           | 8 ++++----
>  2 files changed, 6 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 04d21333130f9..77e1948aef2ff 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -586,6 +586,8 @@ struct intel_connector {
>  
>  			u16 su_w_granularity;
>  			u16 su_y_granularity;
> +
> +			u8 sync_latency;
>  		} psr_caps;
>  	} dp;
>  
> @@ -1740,7 +1742,6 @@ struct intel_psr {
>  	bool psr2_sel_fetch_cff_enabled;
>  	bool su_region_et_enabled;
>  	bool req_psr2_sdp_prior_scanline;
> -	u8 sink_sync_latency;
>  	ktime_t last_entry_attempt;
>  	ktime_t last_exit;
>  	bool sink_not_reliable;
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index e6268d692f89d..bbd1b0e8beecb 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -685,8 +685,7 @@ static void _psr_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *co
>  	connector->dp.psr_caps.support = true;
>  	intel_dp->psr.sink_support = true;
>  
> -	intel_dp->psr.sink_sync_latency =
> -		intel_dp_get_sink_sync_latency(intel_dp);
> +	connector->dp.psr_caps.sync_latency = intel_dp_get_sink_sync_latency(intel_dp);
>  
>  	if (DISPLAY_VER(display) >= 9 &&
>  	    connector->dp.psr_dpcd[0] >= DP_PSR2_WITH_Y_COORD_IS_SUPPORTED) {
> @@ -911,7 +910,7 @@ static u8 psr_compute_idle_frames(struct intel_dp *intel_dp)
>  	 * off-by-one issue that HW has in some cases.
>  	 */
>  	idle_frames = max(6, connector->panel.vbt.psr.idle_frames);
> -	idle_frames = max(idle_frames, intel_dp->psr.sink_sync_latency + 1);
> +	idle_frames = max(idle_frames, connector->dp.psr_caps.sync_latency + 1);
>  
>  	if (drm_WARN_ON(display->drm, idle_frames > 0xf))
>  		idle_frames = 0xf;
> @@ -1006,10 +1005,11 @@ static int psr2_block_count(struct intel_dp *intel_dp)
>  
>  static u8 frames_before_su_entry(struct intel_dp *intel_dp)
>  {
> +	struct intel_connector *connector = intel_dp->attached_connector;
>  	u8 frames_before_su_entry;
>  
>  	frames_before_su_entry = max_t(u8,
> -				       intel_dp->psr.sink_sync_latency + 1,
> +				       connector->dp.psr_caps.sync_latency + 1,
>  				       2);
>  
>  	/* Entry setup frames must be at least 1 less than frames before SU entry */
> -- 
> 2.43.0
> 

✓ i915.CI.BAT: success for Move PSR/Panel Replay sink data into intel_connector

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 2372 bytes --]

== Series Details ==

Series: Move PSR/Panel Replay sink data into intel_connector
URL   : https://patchwork.freedesktop.org/series/157899/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_17579 -> Patchwork_157899v1
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/index.html

Participating hosts (45 -> 44)
------------------------------

  Missing    (1): fi-snb-2520m 

Known issues
------------

  Here are the changes found in Patchwork_157899v1 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_selftest@live@workarounds:
    - bat-arlh-3:         [PASS][1] -> [DMESG-FAIL][2] ([i915#12061]) +1 other test dmesg-fail
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/bat-arlh-3/igt@i915_selftest@live@workarounds.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/bat-arlh-3/igt@i915_selftest@live@workarounds.html
    - bat-dg2-14:         [PASS][3] -> [DMESG-FAIL][4] ([i915#12061]) +1 other test dmesg-fail
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/bat-dg2-14/igt@i915_selftest@live@workarounds.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/bat-dg2-14/igt@i915_selftest@live@workarounds.html

  
#### Possible fixes ####

  * igt@i915_selftest@live@workarounds:
    - bat-arls-5:         [DMESG-FAIL][5] ([i915#12061]) -> [PASS][6] +1 other test pass
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/bat-arls-5/igt@i915_selftest@live@workarounds.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/bat-arls-5/igt@i915_selftest@live@workarounds.html

  
  [i915#12061]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12061


Build changes
-------------

  * Linux: CI_DRM_17579 -> Patchwork_157899v1

  CI-20190529: 20190529
  CI_DRM_17579: ed157ca0caebebe3af6d38ca0fb64a403c84ce77 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_8636: 254cd102396ff95d61f2ebe49fc09128878bf483 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_157899v1: ed157ca0caebebe3af6d38ca0fb64a403c84ce77 @ git://anongit.freedesktop.org/gfx-ci/linux

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/index.html

[-- Attachment #2: Type: text/html, Size: 3142 bytes --]

✗ i915.CI.Full: failure for Move PSR/Panel Replay sink data into intel_connector

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 51800 bytes --]

== Series Details ==

Series: Move PSR/Panel Replay sink data into intel_connector
URL   : https://patchwork.freedesktop.org/series/157899/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_17579_full -> Patchwork_157899v1_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_157899v1_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_157899v1_full, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (10 -> 10)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_157899v1_full:

### IGT changes ###

#### Possible regressions ####

  * igt@gem_exec_suspend@basic-s0:
    - shard-mtlp:         [PASS][1] -> [ABORT][2] +3 other tests abort
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-mtlp-3/igt@gem_exec_suspend@basic-s0.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-mtlp-6/igt@gem_exec_suspend@basic-s0.html

  * igt@gem_softpin@noreloc-s3:
    - shard-glk:          NOTRUN -> [ABORT][3] +1 other test abort
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-glk6/igt@gem_softpin@noreloc-s3.html
    - shard-dg2:          [PASS][4] -> [ABORT][5]
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-dg2-7/igt@gem_softpin@noreloc-s3.html
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-dg2-11/igt@gem_softpin@noreloc-s3.html

  * igt@i915_suspend@basic-s3-without-i915:
    - shard-snb:          [PASS][6] -> [ABORT][7]
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-snb6/igt@i915_suspend@basic-s3-without-i915.html
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-snb5/igt@i915_suspend@basic-s3-without-i915.html
    - shard-dg1:          [PASS][8] -> [ABORT][9]
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-dg1-12/igt@i915_suspend@basic-s3-without-i915.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-dg1-14/igt@i915_suspend@basic-s3-without-i915.html

  * igt@i915_suspend@fence-restore-untiled:
    - shard-glk10:        NOTRUN -> [ABORT][10] +4 other tests abort
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-glk10/igt@i915_suspend@fence-restore-untiled.html

  * igt@kms_async_flips@invalid-async-flip@pipe-b-edp-1:
    - shard-mtlp:         NOTRUN -> [FAIL][11] +2 other tests fail
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-mtlp-2/igt@kms_async_flips@invalid-async-flip@pipe-b-edp-1.html

  * igt@kms_cursor_crc@cursor-suspend@pipe-a-hdmi-a-1:
    - shard-tglu-1:       NOTRUN -> [ABORT][12] +1 other test abort
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-tglu-1/igt@kms_cursor_crc@cursor-suspend@pipe-a-hdmi-a-1.html

  * igt@kms_cursor_crc@cursor-suspend@pipe-a-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [ABORT][13]
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-rkl-1/igt@kms_cursor_crc@cursor-suspend@pipe-a-hdmi-a-2.html

  * igt@kms_pipe_crc_basic@suspend-read-crc@pipe-a-dp-3:
    - shard-dg2:          NOTRUN -> [ABORT][14]
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-dg2-11/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-a-dp-3.html

  * igt@kms_pipe_crc_basic@suspend-read-crc@pipe-a-hdmi-a-3:
    - shard-dg1:          NOTRUN -> [ABORT][15] +1 other test abort
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-dg1-12/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-a-hdmi-a-3.html

  * igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b:
    - shard-tglu:         [PASS][16] -> [ABORT][17]
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-tglu-3/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b.html
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-tglu-4/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b.html

  * igt@kms_vblank@ts-continuation-suspend@pipe-a-hdmi-a-1:
    - shard-glk:          [PASS][18] -> [ABORT][19]
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-glk1/igt@kms_vblank@ts-continuation-suspend@pipe-a-hdmi-a-1.html
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-glk5/igt@kms_vblank@ts-continuation-suspend@pipe-a-hdmi-a-1.html

  
#### Warnings ####

  * igt@kms_vblank@ts-continuation-suspend:
    - shard-glk:          [INCOMPLETE][20] ([i915#12276]) -> [ABORT][21]
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-glk1/igt@kms_vblank@ts-continuation-suspend.html
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-glk5/igt@kms_vblank@ts-continuation-suspend.html

  
Known issues
------------

  Here are the changes found in Patchwork_157899v1_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_ctx_isolation@preservation-s3@rcs0:
    - shard-glk:          NOTRUN -> [INCOMPLETE][22] ([i915#13356]) +1 other test incomplete
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-glk3/igt@gem_ctx_isolation@preservation-s3@rcs0.html

  * igt@gem_eio@hibernate:
    - shard-tglu:         NOTRUN -> [ABORT][23] ([i915#7975])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-tglu-2/igt@gem_eio@hibernate.html

  * igt@gem_exec_balancer@bonded-true-hang:
    - shard-mtlp:         NOTRUN -> [SKIP][24] ([i915#4812])
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-mtlp-2/igt@gem_exec_balancer@bonded-true-hang.html

  * igt@gem_exec_reloc@basic-wc-gtt:
    - shard-mtlp:         NOTRUN -> [SKIP][25] ([i915#3281]) +1 other test skip
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-mtlp-2/igt@gem_exec_reloc@basic-wc-gtt.html

  * igt@gem_exec_schedule@preempt-queue-contexts:
    - shard-mtlp:         NOTRUN -> [SKIP][26] ([i915#4537] / [i915#4812])
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-mtlp-2/igt@gem_exec_schedule@preempt-queue-contexts.html

  * igt@gem_lmem_swapping@verify:
    - shard-mtlp:         NOTRUN -> [SKIP][27] ([i915#4613]) +1 other test skip
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-mtlp-2/igt@gem_lmem_swapping@verify.html

  * igt@gem_lmem_swapping@verify-random-ccs:
    - shard-glk:          NOTRUN -> [SKIP][28] ([i915#4613])
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-glk9/igt@gem_lmem_swapping@verify-random-ccs.html

  * igt@gem_mmap_gtt@basic:
    - shard-mtlp:         NOTRUN -> [SKIP][29] ([i915#4077]) +3 other tests skip
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-mtlp-2/igt@gem_mmap_gtt@basic.html

  * igt@gem_mmap_wc@bad-size:
    - shard-mtlp:         NOTRUN -> [SKIP][30] ([i915#4083])
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-mtlp-2/igt@gem_mmap_wc@bad-size.html

  * igt@gem_render_copy@yf-tiled-ccs-to-yf-tiled:
    - shard-mtlp:         NOTRUN -> [SKIP][31] ([i915#8428]) +1 other test skip
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-mtlp-2/igt@gem_render_copy@yf-tiled-ccs-to-yf-tiled.html

  * igt@gem_userptr_blits@relocations:
    - shard-mtlp:         NOTRUN -> [SKIP][32] ([i915#3281] / [i915#3297])
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-mtlp-2/igt@gem_userptr_blits@relocations.html

  * igt@gen9_exec_parse@secure-batches:
    - shard-mtlp:         NOTRUN -> [SKIP][33] ([i915#2856])
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-mtlp-2/igt@gen9_exec_parse@secure-batches.html

  * igt@i915_drm_fdinfo@most-busy-idle-check-all:
    - shard-mtlp:         NOTRUN -> [SKIP][34] ([i915#14073]) +6 other tests skip
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-mtlp-2/igt@i915_drm_fdinfo@most-busy-idle-check-all.html

  * igt@kms_addfb_basic@framebuffer-vs-set-tiling:
    - shard-mtlp:         NOTRUN -> [SKIP][35] ([i915#4212])
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-mtlp-2/igt@kms_addfb_basic@framebuffer-vs-set-tiling.html

  * igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels:
    - shard-glk:          NOTRUN -> [SKIP][36] ([i915#1769])
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-glk6/igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels.html

  * igt@kms_big_fb@4-tiled-8bpp-rotate-90:
    - shard-tglu:         NOTRUN -> [SKIP][37] ([i915#5286])
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-tglu-2/igt@kms_big_fb@4-tiled-8bpp-rotate-90.html

  * igt@kms_big_fb@x-tiled-8bpp-rotate-270:
    - shard-mtlp:         NOTRUN -> [SKIP][38] +6 other tests skip
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-mtlp-2/igt@kms_big_fb@x-tiled-8bpp-rotate-270.html

  * igt@kms_ccs@bad-aux-stride-y-tiled-gen12-rc-ccs@pipe-d-hdmi-a-1:
    - shard-dg2:          NOTRUN -> [SKIP][39] ([i915#10307] / [i915#10434] / [i915#6095]) +1 other test skip
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-dg2-4/igt@kms_ccs@bad-aux-stride-y-tiled-gen12-rc-ccs@pipe-d-hdmi-a-1.html

  * igt@kms_ccs@bad-pixel-format-yf-tiled-ccs@pipe-a-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [SKIP][40] ([i915#14544] / [i915#6095]) +3 other tests skip
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-rkl-6/igt@kms_ccs@bad-pixel-format-yf-tiled-ccs@pipe-a-hdmi-a-2.html

  * igt@kms_ccs@bad-pixel-format-yf-tiled-ccs@pipe-c-hdmi-a-1:
    - shard-glk10:        NOTRUN -> [SKIP][41] +47 other tests skip
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-glk10/igt@kms_ccs@bad-pixel-format-yf-tiled-ccs@pipe-c-hdmi-a-1.html

  * igt@kms_ccs@bad-pixel-format-yf-tiled-ccs@pipe-c-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [SKIP][42] ([i915#14098] / [i915#14544] / [i915#6095]) +1 other test skip
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-rkl-6/igt@kms_ccs@bad-pixel-format-yf-tiled-ccs@pipe-c-hdmi-a-2.html

  * igt@kms_ccs@crc-primary-rotation-180-4-tiled-dg2-rc-ccs-cc:
    - shard-tglu:         NOTRUN -> [SKIP][43] ([i915#6095]) +4 other tests skip
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-tglu-2/igt@kms_ccs@crc-primary-rotation-180-4-tiled-dg2-rc-ccs-cc.html

  * igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-mc-ccs@pipe-c-hdmi-a-2:
    - shard-glk:          NOTRUN -> [SKIP][44] +137 other tests skip
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-glk3/igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-mc-ccs@pipe-c-hdmi-a-2.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-mc-ccs@pipe-c-hdmi-a-4:
    - shard-dg1:          NOTRUN -> [SKIP][45] ([i915#6095]) +43 other tests skip
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-dg1-18/igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-mc-ccs@pipe-c-hdmi-a-4.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-rc-ccs-cc@pipe-b-hdmi-a-3:
    - shard-dg2:          NOTRUN -> [SKIP][46] ([i915#6095]) +3 other tests skip
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-dg2-6/igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-rc-ccs-cc@pipe-b-hdmi-a-3.html

  * igt@kms_ccs@crc-primary-suspend-yf-tiled-ccs@pipe-d-edp-1:
    - shard-mtlp:         NOTRUN -> [SKIP][47] ([i915#6095]) +9 other tests skip
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-mtlp-2/igt@kms_ccs@crc-primary-suspend-yf-tiled-ccs@pipe-d-edp-1.html

  * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-dg2-rc-ccs@pipe-b-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [SKIP][48] ([i915#6095]) +19 other tests skip
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-rkl-4/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-dg2-rc-ccs@pipe-b-hdmi-a-2.html

  * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-dg2-rc-ccs@pipe-c-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [SKIP][49] ([i915#14098] / [i915#6095]) +9 other tests skip
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-rkl-4/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-dg2-rc-ccs@pipe-c-hdmi-a-2.html

  * igt@kms_ccs@crc-sprite-planes-basic-y-tiled-gen12-rc-ccs-cc@pipe-c-dp-3:
    - shard-dg2:          NOTRUN -> [SKIP][50] ([i915#10307] / [i915#6095]) +61 other tests skip
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-dg2-11/igt@kms_ccs@crc-sprite-planes-basic-y-tiled-gen12-rc-ccs-cc@pipe-c-dp-3.html

  * igt@kms_chamelium_audio@dp-audio:
    - shard-mtlp:         NOTRUN -> [SKIP][51] ([i915#11151] / [i915#7828]) +1 other test skip
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-mtlp-2/igt@kms_chamelium_audio@dp-audio.html

  * igt@kms_chamelium_edid@dp-edid-resolution-list:
    - shard-tglu:         NOTRUN -> [SKIP][52] ([i915#11151] / [i915#7828])
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-tglu-2/igt@kms_chamelium_edid@dp-edid-resolution-list.html

  * igt@kms_cursor_crc@cursor-offscreen-32x10:
    - shard-mtlp:         NOTRUN -> [SKIP][53] ([i915#3555] / [i915#8814]) +2 other tests skip
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-mtlp-2/igt@kms_cursor_crc@cursor-offscreen-32x10.html

  * igt@kms_cursor_crc@cursor-onscreen-32x32:
    - shard-tglu:         NOTRUN -> [SKIP][54] ([i915#3555])
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-tglu-2/igt@kms_cursor_crc@cursor-onscreen-32x32.html

  * igt@kms_cursor_crc@cursor-sliding-256x85:
    - shard-rkl:          [PASS][55] -> [FAIL][56] ([i915#13566])
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-rkl-7/igt@kms_cursor_crc@cursor-sliding-256x85.html
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-rkl-8/igt@kms_cursor_crc@cursor-sliding-256x85.html

  * igt@kms_cursor_crc@cursor-sliding-256x85@pipe-a-hdmi-a-1:
    - shard-rkl:          NOTRUN -> [FAIL][57] ([i915#13566])
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-rkl-8/igt@kms_cursor_crc@cursor-sliding-256x85@pipe-a-hdmi-a-1.html

  * igt@kms_cursor_crc@cursor-suspend:
    - shard-glk:          NOTRUN -> [INCOMPLETE][58] ([i915#12358] / [i915#14152] / [i915#7882])
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-glk1/igt@kms_cursor_crc@cursor-suspend.html

  * igt@kms_cursor_crc@cursor-suspend@pipe-a-hdmi-a-1:
    - shard-glk:          NOTRUN -> [INCOMPLETE][59] ([i915#12358] / [i915#14152])
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-glk1/igt@kms_cursor_crc@cursor-suspend@pipe-a-hdmi-a-1.html

  * igt@kms_cursor_legacy@cursorb-vs-flipa-legacy:
    - shard-mtlp:         NOTRUN -> [SKIP][60] ([i915#9809])
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-mtlp-2/igt@kms_cursor_legacy@cursorb-vs-flipa-legacy.html

  * igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [SKIP][61] ([i915#14544] / [i915#3804])
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-rkl-6/igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-2.html

  * igt@kms_dsc@dsc-with-bpc-formats:
    - shard-tglu:         NOTRUN -> [SKIP][62] ([i915#3555] / [i915#3840])
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-tglu-2/igt@kms_dsc@dsc-with-bpc-formats.html

  * igt@kms_flip@2x-absolute-wf_vblank:
    - shard-mtlp:         NOTRUN -> [SKIP][63] ([i915#3637] / [i915#9934])
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-mtlp-2/igt@kms_flip@2x-absolute-wf_vblank.html

  * igt@kms_flip@2x-flip-vs-dpms-on-nop:
    - shard-mtlp:         NOTRUN -> [SKIP][64] ([i915#9934])
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-mtlp-2/igt@kms_flip@2x-flip-vs-dpms-on-nop.html

  * igt@kms_flip@2x-modeset-vs-vblank-race:
    - shard-tglu:         NOTRUN -> [SKIP][65] ([i915#3637] / [i915#9934]) +1 other test skip
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-tglu-2/igt@kms_flip@2x-modeset-vs-vblank-race.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@a-hdmi-a2:
    - shard-glk:          NOTRUN -> [FAIL][66] ([i915#13027]) +1 other test fail
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-glk9/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-hdmi-a2.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling:
    - shard-mtlp:         NOTRUN -> [SKIP][67] ([i915#2672] / [i915#3555] / [i915#8813])
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-mtlp-2/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling@pipe-a-default-mode:
    - shard-mtlp:         NOTRUN -> [SKIP][68] ([i915#2672] / [i915#8813])
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-mtlp-2/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling@pipe-a-default-mode.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-gtt:
    - shard-tglu:         NOTRUN -> [SKIP][69] +5 other tests skip
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-tglu-2/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-mmap-cpu:
    - shard-tglu-1:       NOTRUN -> [SKIP][70] +1 other test skip
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-tglu-1/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-mmap-cpu.html

  * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-render:
    - shard-mtlp:         NOTRUN -> [SKIP][71] ([i915#1825]) +6 other tests skip
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-mtlp-2/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@psr-modesetfrombusy:
    - shard-tglu:         NOTRUN -> [SKIP][72] ([i915#15102]) +2 other tests skip
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-tglu-2/igt@kms_frontbuffer_tracking@psr-modesetfrombusy.html

  * igt@kms_frontbuffer_tracking@psr-rgb565-draw-mmap-gtt:
    - shard-mtlp:         NOTRUN -> [SKIP][73] ([i915#8708]) +1 other test skip
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-mtlp-2/igt@kms_frontbuffer_tracking@psr-rgb565-draw-mmap-gtt.html

  * igt@kms_hdr@invalid-metadata-sizes:
    - shard-mtlp:         NOTRUN -> [SKIP][74] ([i915#12713] / [i915#3555] / [i915#8228])
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-mtlp-2/igt@kms_hdr@invalid-metadata-sizes.html

  * igt@kms_hdr@static-toggle:
    - shard-dg2:          [PASS][75] -> [SKIP][76] ([i915#3555] / [i915#8228])
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-dg2-11/igt@kms_hdr@static-toggle.html
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-dg2-7/igt@kms_hdr@static-toggle.html

  * igt@kms_joiner@invalid-modeset-force-big-joiner:
    - shard-dg2:          [PASS][77] -> [SKIP][78] ([i915#10656] / [i915#12388])
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-dg2-11/igt@kms_joiner@invalid-modeset-force-big-joiner.html
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-dg2-7/igt@kms_joiner@invalid-modeset-force-big-joiner.html

  * igt@kms_pm_dc@dc5-dpms-negative:
    - shard-mtlp:         NOTRUN -> [SKIP][79] ([i915#13441])
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-mtlp-2/igt@kms_pm_dc@dc5-dpms-negative.html

  * igt@kms_pm_rpm@system-suspend-modeset:
    - shard-glk:          NOTRUN -> [ABORT][80] ([i915#10553])
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-glk6/igt@kms_pm_rpm@system-suspend-modeset.html

  * igt@kms_psr2_sf@fbc-pr-overlay-plane-update-sf-dmg-area:
    - shard-glk:          NOTRUN -> [SKIP][81] ([i915#11520]) +5 other tests skip
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-glk9/igt@kms_psr2_sf@fbc-pr-overlay-plane-update-sf-dmg-area.html

  * igt@kms_psr2_sf@fbc-psr2-cursor-plane-update-sf:
    - shard-tglu:         NOTRUN -> [SKIP][82] ([i915#11520])
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-tglu-2/igt@kms_psr2_sf@fbc-psr2-cursor-plane-update-sf.html

  * igt@kms_psr2_su@frontbuffer-xrgb8888:
    - shard-mtlp:         NOTRUN -> [SKIP][83] ([i915#4348])
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-mtlp-2/igt@kms_psr2_su@frontbuffer-xrgb8888.html

  * igt@kms_psr@fbc-psr2-sprite-mmap-cpu@edp-1:
    - shard-mtlp:         NOTRUN -> [SKIP][84] ([i915#9688]) +1 other test skip
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-mtlp-2/igt@kms_psr@fbc-psr2-sprite-mmap-cpu@edp-1.html

  * igt@kms_psr@fbc-psr2-sprite-render:
    - shard-tglu:         NOTRUN -> [SKIP][85] ([i915#9732])
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-tglu-2/igt@kms_psr@fbc-psr2-sprite-render.html

  * igt@kms_rotation_crc@primary-4-tiled-reflect-x-180:
    - shard-tglu:         NOTRUN -> [SKIP][86] ([i915#5289])
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-tglu-2/igt@kms_rotation_crc@primary-4-tiled-reflect-x-180.html

  * igt@kms_sharpness_filter@filter-formats:
    - shard-mtlp:         NOTRUN -> [SKIP][87] ([i915#15232])
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-mtlp-2/igt@kms_sharpness_filter@filter-formats.html

  * igt@kms_sharpness_filter@filter-scaler-upscale:
    - shard-tglu:         NOTRUN -> [SKIP][88] ([i915#15232])
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-tglu-2/igt@kms_sharpness_filter@filter-scaler-upscale.html

  * igt@kms_vrr@flip-suspend:
    - shard-mtlp:         NOTRUN -> [SKIP][89] ([i915#3555] / [i915#8808])
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-mtlp-2/igt@kms_vrr@flip-suspend.html

  * igt@kms_writeback@writeback-check-output:
    - shard-glk:          NOTRUN -> [SKIP][90] ([i915#2437])
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-glk6/igt@kms_writeback@writeback-check-output.html

  * igt@prime_vgem@basic-fence-read:
    - shard-mtlp:         NOTRUN -> [SKIP][91] ([i915#3708])
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-mtlp-2/igt@prime_vgem@basic-fence-read.html

  
#### Possible fixes ####

  * igt@gem_workarounds@suspend-resume-context:
    - shard-mtlp:         [ABORT][92] -> [PASS][93]
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-mtlp-5/igt@gem_workarounds@suspend-resume-context.html
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-mtlp-2/igt@gem_workarounds@suspend-resume-context.html

  * igt@i915_suspend@fence-restore-tiled2untiled:
    - shard-glk:          [ABORT][94] -> [PASS][95]
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-glk6/igt@i915_suspend@fence-restore-tiled2untiled.html
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-glk3/igt@i915_suspend@fence-restore-tiled2untiled.html

  * igt@kms_cursor_crc@cursor-sliding-256x85:
    - shard-tglu:         [FAIL][96] ([i915#13566]) -> [PASS][97] +1 other test pass
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-tglu-4/igt@kms_cursor_crc@cursor-sliding-256x85.html
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-tglu-9/igt@kms_cursor_crc@cursor-sliding-256x85.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-blt:
    - shard-dg2:          [FAIL][98] ([i915#6880]) -> [PASS][99]
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-dg2-6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-blt.html
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-dg2-3/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-blt.html

  * igt@kms_pipe_crc_basic@suspend-read-crc@pipe-b-hdmi-a-1:
    - shard-snb:          [INCOMPLETE][100] -> [PASS][101]
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-snb1/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-b-hdmi-a-1.html
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-snb6/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-b-hdmi-a-1.html

  * igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a:
    - shard-tglu:         [ABORT][102] -> [PASS][103]
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-tglu-3/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a.html
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-tglu-4/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a.html

  * igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b:
    - shard-rkl:          [INCOMPLETE][104] ([i915#14412]) -> [PASS][105]
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-rkl-6/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b.html
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-rkl-2/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b.html
    - shard-mtlp:         [INCOMPLETE][106] ([i915#13026]) -> [PASS][107]
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-mtlp-2/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b.html
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-mtlp-6/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b.html

  * igt@kms_pm_rpm@modeset-non-lpsp:
    - shard-rkl:          [SKIP][108] ([i915#15073]) -> [PASS][109]
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-rkl-5/igt@kms_pm_rpm@modeset-non-lpsp.html
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-rkl-3/igt@kms_pm_rpm@modeset-non-lpsp.html

  * igt@kms_vrr@negative-basic:
    - shard-dg2:          [SKIP][110] ([i915#3555] / [i915#9906]) -> [PASS][111]
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-dg2-7/igt@kms_vrr@negative-basic.html
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-dg2-11/igt@kms_vrr@negative-basic.html

  
#### Warnings ####

  * igt@api_intel_bb@object-reloc-purge-cache:
    - shard-rkl:          [SKIP][112] ([i915#14544] / [i915#8411]) -> [SKIP][113] ([i915#8411])
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-rkl-6/igt@api_intel_bb@object-reloc-purge-cache.html
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-rkl-2/igt@api_intel_bb@object-reloc-purge-cache.html

  * igt@gem_ctx_sseu@mmap-args:
    - shard-rkl:          [SKIP][114] ([i915#280]) -> [SKIP][115] ([i915#14544] / [i915#280])
   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-rkl-4/igt@gem_ctx_sseu@mmap-args.html
   [115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-rkl-6/igt@gem_ctx_sseu@mmap-args.html

  * igt@gem_exec_reloc@basic-active:
    - shard-rkl:          [SKIP][116] ([i915#3281]) -> [SKIP][117] ([i915#14544] / [i915#3281])
   [116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-rkl-8/igt@gem_exec_reloc@basic-active.html
   [117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-rkl-6/igt@gem_exec_reloc@basic-active.html

  * igt@gem_lmem_swapping@parallel-random:
    - shard-rkl:          [SKIP][118] ([i915#14544] / [i915#4613]) -> [SKIP][119] ([i915#4613])
   [118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-rkl-6/igt@gem_lmem_swapping@parallel-random.html
   [119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-rkl-2/igt@gem_lmem_swapping@parallel-random.html

  * igt@gem_madvise@dontneed-before-pwrite:
    - shard-rkl:          [SKIP][120] ([i915#14544] / [i915#3282]) -> [SKIP][121] ([i915#3282])
   [120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-rkl-6/igt@gem_madvise@dontneed-before-pwrite.html
   [121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-rkl-2/igt@gem_madvise@dontneed-before-pwrite.html

  * igt@gem_pread@display:
    - shard-rkl:          [SKIP][122] ([i915#3282]) -> [SKIP][123] ([i915#14544] / [i915#3282])
   [122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-rkl-4/igt@gem_pread@display.html
   [123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-rkl-6/igt@gem_pread@display.html

  * igt@gem_userptr_blits@create-destroy-unsync:
    - shard-rkl:          [SKIP][124] ([i915#14544] / [i915#3297]) -> [SKIP][125] ([i915#3297])
   [124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-rkl-6/igt@gem_userptr_blits@create-destroy-unsync.html
   [125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-rkl-2/igt@gem_userptr_blits@create-destroy-unsync.html

  * igt@gen9_exec_parse@batch-invalid-length:
    - shard-rkl:          [SKIP][126] ([i915#14544] / [i915#2527]) -> [SKIP][127] ([i915#2527])
   [126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-rkl-6/igt@gen9_exec_parse@batch-invalid-length.html
   [127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-rkl-2/igt@gen9_exec_parse@batch-invalid-length.html

  * igt@gen9_exec_parse@shadow-peek:
    - shard-rkl:          [SKIP][128] ([i915#2527]) -> [SKIP][129] ([i915#14544] / [i915#2527])
   [128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-rkl-8/igt@gen9_exec_parse@shadow-peek.html
   [129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-rkl-6/igt@gen9_exec_parse@shadow-peek.html

  * igt@i915_pm_freq_api@freq-suspend@gt0:
    - shard-dg2:          [ABORT][130] -> [INCOMPLETE][131] ([i915#13356] / [i915#13820]) +1 other test incomplete
   [130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-dg2-8/igt@i915_pm_freq_api@freq-suspend@gt0.html
   [131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-dg2-4/igt@i915_pm_freq_api@freq-suspend@gt0.html

  * igt@kms_big_fb@4-tiled-64bpp-rotate-270:
    - shard-rkl:          [SKIP][132] ([i915#14544] / [i915#5286]) -> [SKIP][133] ([i915#5286])
   [132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-rkl-6/igt@kms_big_fb@4-tiled-64bpp-rotate-270.html
   [133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-rkl-2/igt@kms_big_fb@4-tiled-64bpp-rotate-270.html

  * igt@kms_big_fb@x-tiled-32bpp-rotate-270:
    - shard-rkl:          [SKIP][134] ([i915#3638]) -> [SKIP][135] ([i915#14544] / [i915#3638]) +1 other test skip
   [134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-rkl-4/igt@kms_big_fb@x-tiled-32bpp-rotate-270.html
   [135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-rkl-6/igt@kms_big_fb@x-tiled-32bpp-rotate-270.html

  * igt@kms_big_fb@yf-tiled-8bpp-rotate-0:
    - shard-rkl:          [SKIP][136] -> [SKIP][137] ([i915#14544])
   [136]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-rkl-4/igt@kms_big_fb@yf-tiled-8bpp-rotate-0.html
   [137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-rkl-6/igt@kms_big_fb@yf-tiled-8bpp-rotate-0.html

  * igt@kms_ccs@bad-pixel-format-4-tiled-dg2-mc-ccs@pipe-a-hdmi-a-2:
    - shard-rkl:          [SKIP][138] ([i915#6095]) -> [SKIP][139] ([i915#14544] / [i915#6095]) +3 other tests skip
   [138]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-rkl-4/igt@kms_ccs@bad-pixel-format-4-tiled-dg2-mc-ccs@pipe-a-hdmi-a-2.html
   [139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-rkl-6/igt@kms_ccs@bad-pixel-format-4-tiled-dg2-mc-ccs@pipe-a-hdmi-a-2.html

  * igt@kms_ccs@ccs-on-another-bo-4-tiled-mtl-rc-ccs-cc:
    - shard-rkl:          [SKIP][140] ([i915#14098] / [i915#14544] / [i915#6095]) -> [SKIP][141] ([i915#14098] / [i915#6095]) +2 other tests skip
   [140]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-rkl-6/igt@kms_ccs@ccs-on-another-bo-4-tiled-mtl-rc-ccs-cc.html
   [141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-rkl-2/igt@kms_ccs@ccs-on-another-bo-4-tiled-mtl-rc-ccs-cc.html

  * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-dg2-mc-ccs:
    - shard-rkl:          [SKIP][142] ([i915#14098] / [i915#6095]) -> [SKIP][143] ([i915#14098] / [i915#14544] / [i915#6095]) +5 other tests skip
   [142]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-rkl-8/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-dg2-mc-ccs.html
   [143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-rkl-6/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-dg2-mc-ccs.html

  * igt@kms_chamelium_frames@hdmi-crc-single:
    - shard-rkl:          [SKIP][144] ([i915#11151] / [i915#14544] / [i915#7828]) -> [SKIP][145] ([i915#11151] / [i915#7828]) +2 other tests skip
   [144]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-rkl-6/igt@kms_chamelium_frames@hdmi-crc-single.html
   [145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-rkl-2/igt@kms_chamelium_frames@hdmi-crc-single.html

  * igt@kms_chamelium_hpd@hdmi-hpd-enable-disable-mode:
    - shard-rkl:          [SKIP][146] ([i915#11151] / [i915#7828]) -> [SKIP][147] ([i915#11151] / [i915#14544] / [i915#7828])
   [146]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-rkl-4/igt@kms_chamelium_hpd@hdmi-hpd-enable-disable-mode.html
   [147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-rkl-6/igt@kms_chamelium_hpd@hdmi-hpd-enable-disable-mode.html

  * igt@kms_content_protection@legacy:
    - shard-dg2:          [FAIL][148] ([i915#7173]) -> [SKIP][149] ([i915#7118] / [i915#9424])
   [148]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-dg2-11/igt@kms_content_protection@legacy.html
   [149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-dg2-7/igt@kms_content_protection@legacy.html

  * igt@kms_content_protection@lic-type-0:
    - shard-dg2:          [FAIL][150] ([i915#7173]) -> [SKIP][151] ([i915#9424])
   [150]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-dg2-11/igt@kms_content_protection@lic-type-0.html
   [151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-dg2-6/igt@kms_content_protection@lic-type-0.html

  * igt@kms_content_protection@mei-interface:
    - shard-dg1:          [SKIP][152] ([i915#9433]) -> [SKIP][153] ([i915#9424])
   [152]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-dg1-13/igt@kms_content_protection@mei-interface.html
   [153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-dg1-17/igt@kms_content_protection@mei-interface.html

  * igt@kms_cursor_crc@cursor-offscreen-32x32:
    - shard-rkl:          [SKIP][154] ([i915#14544] / [i915#3555]) -> [SKIP][155] ([i915#3555])
   [154]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-rkl-6/igt@kms_cursor_crc@cursor-offscreen-32x32.html
   [155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-rkl-2/igt@kms_cursor_crc@cursor-offscreen-32x32.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size:
    - shard-rkl:          [SKIP][156] ([i915#4103]) -> [SKIP][157] ([i915#14544] / [i915#4103])
   [156]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-rkl-4/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size.html
   [157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-rkl-6/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size.html

  * igt@kms_cursor_legacy@cursora-vs-flipb-toggle:
    - shard-rkl:          [SKIP][158] ([i915#14544]) -> [SKIP][159] +2 other tests skip
   [158]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-rkl-6/igt@kms_cursor_legacy@cursora-vs-flipb-toggle.html
   [159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-rkl-2/igt@kms_cursor_legacy@cursora-vs-flipb-toggle.html

  * igt@kms_dither@fb-8bpc-vs-panel-6bpc:
    - shard-rkl:          [SKIP][160] ([i915#3555] / [i915#3804]) -> [SKIP][161] ([i915#14544] / [i915#3555] / [i915#3804])
   [160]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-rkl-8/igt@kms_dither@fb-8bpc-vs-panel-6bpc.html
   [161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-rkl-6/igt@kms_dither@fb-8bpc-vs-panel-6bpc.html

  * igt@kms_dsc@dsc-fractional-bpp:
    - shard-rkl:          [SKIP][162] ([i915#14544] / [i915#3840]) -> [SKIP][163] ([i915#3840])
   [162]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-rkl-6/igt@kms_dsc@dsc-fractional-bpp.html
   [163]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-rkl-2/igt@kms_dsc@dsc-fractional-bpp.html

  * igt@kms_flip@2x-flip-vs-suspend:
    - shard-glk:          [INCOMPLETE][164] ([i915#12745] / [i915#4839] / [i915#6113]) -> [INCOMPLETE][165] ([i915#12745] / [i915#4839])
   [164]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-glk3/igt@kms_flip@2x-flip-vs-suspend.html
   [165]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-glk6/igt@kms_flip@2x-flip-vs-suspend.html

  * igt@kms_flip@2x-flip-vs-suspend@ab-hdmi-a1-hdmi-a2:
    - shard-glk:          [INCOMPLETE][166] ([i915#4839] / [i915#6113]) -> [INCOMPLETE][167] ([i915#4839])
   [166]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-glk3/igt@kms_flip@2x-flip-vs-suspend@ab-hdmi-a1-hdmi-a2.html
   [167]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-glk6/igt@kms_flip@2x-flip-vs-suspend@ab-hdmi-a1-hdmi-a2.html

  * igt@kms_flip@2x-flip-vs-wf_vblank-interruptible:
    - shard-rkl:          [SKIP][168] ([i915#9934]) -> [SKIP][169] ([i915#14544] / [i915#9934])
   [168]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-rkl-4/igt@kms_flip@2x-flip-vs-wf_vblank-interruptible.html
   [169]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-rkl-6/igt@kms_flip@2x-flip-vs-wf_vblank-interruptible.html

  * igt@kms_flip@2x-wf_vblank-ts-check-interruptible:
    - shard-rkl:          [SKIP][170] ([i915#14544] / [i915#9934]) -> [SKIP][171] ([i915#9934])
   [170]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-rkl-6/igt@kms_flip@2x-wf_vblank-ts-check-interruptible.html
   [171]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-rkl-2/igt@kms_flip@2x-wf_vblank-ts-check-interruptible.html

  * igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-upscaling:
    - shard-rkl:          [SKIP][172] ([i915#14544] / [i915#2672] / [i915#3555]) -> [SKIP][173] ([i915#2672] / [i915#3555])
   [172]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-rkl-6/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-upscaling.html
   [173]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-rkl-2/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-upscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-upscaling@pipe-a-valid-mode:
    - shard-rkl:          [SKIP][174] ([i915#14544] / [i915#2672]) -> [SKIP][175] ([i915#2672])
   [174]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-rkl-6/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-upscaling@pipe-a-valid-mode.html
   [175]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-rkl-2/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-upscaling@pipe-a-valid-mode.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-indfb-msflip-blt:
    - shard-rkl:          [SKIP][176] ([i915#1825]) -> [SKIP][177] ([i915#14544] / [i915#1825]) +5 other tests skip
   [176]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-rkl-8/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-indfb-msflip-blt.html
   [177]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-rkl-6/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-indfb-msflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-mmap-cpu:
    - shard-rkl:          [SKIP][178] ([i915#14544] / [i915#1825]) -> [SKIP][179] ([i915#1825]) +4 other tests skip
   [178]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-rkl-6/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-mmap-cpu.html
   [179]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-rkl-2/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-mmap-cpu.html

  * igt@kms_frontbuffer_tracking@fbcpsr-suspend:
    - shard-dg2:          [SKIP][180] ([i915#15102] / [i915#3458]) -> [SKIP][181] ([i915#10433] / [i915#15102] / [i915#3458]) +1 other test skip
   [180]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-dg2-8/igt@kms_frontbuffer_tracking@fbcpsr-suspend.html
   [181]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-dg2-4/igt@kms_frontbuffer_tracking@fbcpsr-suspend.html

  * igt@kms_frontbuffer_tracking@psr-1p-offscreen-pri-shrfb-draw-render:
    - shard-rkl:          [SKIP][182] ([i915#15102]) -> [SKIP][183] ([i915#14544] / [i915#15102])
   [182]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-rkl-8/igt@kms_frontbuffer_tracking@psr-1p-offscreen-pri-shrfb-draw-render.html
   [183]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-rkl-6/igt@kms_frontbuffer_tracking@psr-1p-offscreen-pri-shrfb-draw-render.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-render:
    - shard-rkl:          [SKIP][184] ([i915#15102] / [i915#3023]) -> [SKIP][185] ([i915#14544] / [i915#15102] / [i915#3023])
   [184]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-rkl-4/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-render.html
   [185]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-rkl-6/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@psr-rgb101010-draw-render:
    - shard-rkl:          [SKIP][186] ([i915#14544] / [i915#15102] / [i915#3023]) -> [SKIP][187] ([i915#15102] / [i915#3023]) +2 other tests skip
   [186]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-rkl-6/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-render.html
   [187]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-rkl-2/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-render.html

  * igt@kms_plane_lowres@tiling-yf:
    - shard-rkl:          [SKIP][188] ([i915#3555]) -> [SKIP][189] ([i915#14544] / [i915#3555]) +1 other test skip
   [188]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-rkl-8/igt@kms_plane_lowres@tiling-yf.html
   [189]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-rkl-6/igt@kms_plane_lowres@tiling-yf.html

  * igt@kms_psr2_sf@pr-overlay-plane-move-continuous-exceed-sf:
    - shard-rkl:          [SKIP][190] ([i915#11520] / [i915#14544]) -> [SKIP][191] ([i915#11520]) +1 other test skip
   [190]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-rkl-6/igt@kms_psr2_sf@pr-overlay-plane-move-continuous-exceed-sf.html
   [191]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-rkl-2/igt@kms_psr2_sf@pr-overlay-plane-move-continuous-exceed-sf.html

  * igt@kms_psr@fbc-psr-sprite-blt:
    - shard-rkl:          [SKIP][192] ([i915#1072] / [i915#14544] / [i915#9732]) -> [SKIP][193] ([i915#1072] / [i915#9732]) +2 other tests skip
   [192]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-rkl-6/igt@kms_psr@fbc-psr-sprite-blt.html
   [193]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-rkl-2/igt@kms_psr@fbc-psr-sprite-blt.html

  * igt@kms_psr@psr2-primary-mmap-gtt:
    - shard-rkl:          [SKIP][194] ([i915#1072] / [i915#9732]) -> [SKIP][195] ([i915#1072] / [i915#14544] / [i915#9732]) +3 other tests skip
   [194]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-rkl-4/igt@kms_psr@psr2-primary-mmap-gtt.html
   [195]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-rkl-6/igt@kms_psr@psr2-primary-mmap-gtt.html

  * igt@kms_sharpness_filter@filter-scaler-downscale:
    - shard-rkl:          [SKIP][196] ([i915#14544] / [i915#15232]) -> [SKIP][197] ([i915#15232])
   [196]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-rkl-6/igt@kms_sharpness_filter@filter-scaler-downscale.html
   [197]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/shard-rkl-2/igt@kms_sharpness_filter@filter-scaler-downscale.html

  
  [i915#10307]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10307
  [i915#10433]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10433
  [i915#10434]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10434
  [i915#10553]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10553
  [i915#10656]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10656
  [i915#1072]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1072
  [i915#11151]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11151
  [i915#11520]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11520
  [i915#12276]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12276
  [i915#12358]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12358
  [i915#12388]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12388
  [i915#12713]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12713
  [i915#12745]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12745
  [i915#13026]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13026
  [i915#13027]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13027
  [i915#13356]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13356
  [i915#13441]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13441
  [i915#13566]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13566
  [i915#13820]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13820
  [i915#14073]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14073
  [i915#14098]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14098
  [i915#14152]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14152
  [i915#14412]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14412
  [i915#14544]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14544
  [i915#15073]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15073
  [i915#15102]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15102
  [i915#15232]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15232
  [i915#1769]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1769
  [i915#1825]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1825
  [i915#2437]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2437
  [i915#2527]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2527
  [i915#2672]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2672
  [i915#280]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/280
  [i915#2856]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2856
  [i915#3023]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3023
  [i915#3281]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3281
  [i915#3282]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3282
  [i915#3297]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3297
  [i915#3458]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3458
  [i915#3555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3555
  [i915#3637]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3637
  [i915#3638]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3638
  [i915#3708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3708
  [i915#3804]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3804
  [i915#3840]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3840
  [i915#4077]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4077
  [i915#4083]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4083
  [i915#4103]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4103
  [i915#4212]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4212
  [i915#4348]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4348
  [i915#4537]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4537
  [i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613
  [i915#4812]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4812
  [i915#4839]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4839
  [i915#5286]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5286
  [i915#5289]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5289
  [i915#6095]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6095
  [i915#6113]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6113
  [i915#6880]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6880
  [i915#7118]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7118
  [i915#7173]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7173
  [i915#7828]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7828
  [i915#7882]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7882
  [i915#7975]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7975
  [i915#8228]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8228
  [i915#8411]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8411
  [i915#8428]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8428
  [i915#8708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8708
  [i915#8808]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8808
  [i915#8813]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8813
  [i915#8814]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8814
  [i915#9424]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9424
  [i915#9433]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9433
  [i915#9688]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9688
  [i915#9732]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9732
  [i915#9809]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9809
  [i915#9906]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9906
  [i915#9934]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9934


Build changes
-------------

  * Linux: CI_DRM_17579 -> Patchwork_157899v1

  CI-20190529: 20190529
  CI_DRM_17579: ed157ca0caebebe3af6d38ca0fb64a403c84ce77 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_8636: 254cd102396ff95d61f2ebe49fc09128878bf483 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_157899v1: ed157ca0caebebe3af6d38ca0fb64a403c84ce77 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157899v1/index.html

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