From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jesse Barnes Subject: Re: [PATCH] drm/i915: disable rc6 on Cantiga and Crestline Date: Sat, 25 Dec 2010 12:35:00 -0800 Message-ID: References: <1293251374-2565-1-git-send-email-jbarnes@virtuousgeek.org> <0d30dc$kil0gl@orsmga001.jf.intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from oproxy2-pub.bluehost.com (oproxy2-pub.bluehost.com [67.222.39.60]) by gabe.freedesktop.org (Postfix) with SMTP id E931A9E730 for ; Sat, 25 Dec 2010 12:34:50 -0800 (PST) In-Reply-To: <0d30dc$kil0gl@orsmga001.jf.intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Chris Wilson , intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org Yeah, we should be able to get it working, but the MI_SET_CONTEXT is failing. I tried removing the extended save/restore and suspend flush, but things still hung at load. We probably need to init some DRPS state as well... "Chris Wilson" wrote: >On Fri, 24 Dec 2010 20:29:34 -0800, Jesse Barnes > wrote: >> The Ironlake code won't work on these old chips, so disable it to >avoid >> hanging older systems. > >But AFAICS, pwrctxa is enabled for crestline/cantiga. Any info on >whether >that's true? >-Chris > >-- >Chris Wilson, Intel Open Source Technology Centre -- Jesse Barnes, Intel Open Source Technology Center