Re: [Intel-gfx] [v5 1/2] drm/i915/display/tgl: Disable FBC with PSR2

["Shankar, Uma" <uma.shankar@intel.com>]

> -----Original Message-----
> From: Souza, Jose <jose.souza@intel.com>
> Sent: Tuesday, December 1, 2020 10:13 PM
> To: Shankar, Uma <uma.shankar@intel.com>; intel-gfx@lists.freedesktop.org
> Cc: ville.syrjala@linux.intel.com
> Subject: Re: [v5 1/2] drm/i915/display/tgl: Disable FBC with PSR2
> 
> On Tue, 2020-12-01 at 22:17 +0530, Uma Shankar wrote:
> > There are some corner cases wrt underrun when we enable FBC with PSR2
> > on TGL. Recommendation from hardware is to keep this combination
> > disabled.
> >
> > Bspec: 50422 HSD: 14010260002
> >
> > v2: Added psr2 enabled check from crtc_state (Anshuman) Added Bspec
> > link and HSD referneces (Jose)
> >
> > v3: Moved the logic to disable fbc to intel_fbc_update_state_cache and
> > removed the crtc->config usages, as per Ville's recommendation.
> >
> > v4: Introduced a variable in fbc state_cache instead of the earlier
> > plane.visible WA, as suggested by Jose.
> >
> > v5: Dropped an extra check for fbc in intel_fbc_enable and addressed
> > review comments by Jose.
> >
> > Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_fbc.c | 12 ++++++++++++
> >  drivers/gpu/drm/i915/i915_drv.h          |  1 +
> >  2 files changed, 13 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
> > b/drivers/gpu/drm/i915/display/intel_fbc.c
> > index a5b072816a7b..611cadc5c70a 100644
> > --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> > @@ -742,6 +742,8 @@ static void intel_fbc_update_state_cache(struct
> intel_crtc *crtc,
> >  		cache->fence_id = plane_state->vma->fence->id;
> >  	else
> >  		cache->fence_id = -1;
> > +
> > +	cache->psr2_active = crtc_state->has_psr2;
> >  }
> >
> >
> >
> >
> >  static bool intel_fbc_cfb_size_changed(struct drm_i915_private
> > *dev_priv) @@ -799,6 +801,16 @@ static bool intel_fbc_can_activate(struct
> intel_crtc *crtc)
> >  	struct intel_fbc *fbc = &dev_priv->fbc;
> >  	struct intel_fbc_state_cache *cache = &fbc->state_cache;
> >
> >
> >
> >
> > +	/*
> > +	 * Tigerlake is not supporting FBC with PSR2.
> > +	 * Recommendation is to keep this combination disabled
> > +	 * Bspec: 50422 HSD: 14010260002
> > +	 */
> > +	if (fbc->state_cache.psr2_active && IS_TIGERLAKE(dev_priv)) {
> > +		fbc->no_fbc_reason = "not supported with PSR2";
> > +		return false;
> > +	}
> 
> Nitpick: all new restrictions are added at the bottom lets follow it.

Sure, will update that.

> With this change you can add my rvb in both patches.
> Reviewed-by: José Roberto de Souza <jose.souza@intel.com>

Thanks Jose for the review.

Regards,
Uma Shankar
> 
> 
> > +
> >  	if (!intel_fbc_can_enable(dev_priv))
> >  		return false;
> >
> >
> >
> >
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > b/drivers/gpu/drm/i915/i915_drv.h index 15be8debae54..f4e08c1a5867
> > 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -416,6 +416,7 @@ struct intel_fbc {
> >  		u16 gen9_wa_cfb_stride;
> >  		u16 interval;
> >  		s8 fence_id;
> > +		bool psr2_active;
> >  	} state_cache;
> >
> >
> >
> >
> >  	/*

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