From: Madhav Chauhan <madhav.chauhan@intel.com>
To: "Jani Nikula" <jani.nikula@intel.com>,
"Ville Syrjälä" <ville.syrjala@linux.intel.com>
Cc: "intel-gfx@lists.freedesktop.org"
<intel-gfx@lists.freedesktop.org>,
"Zanoni, Paulo R" <paulo.r.zanoni@intel.com>,
"Vivi, Rodrigo" <rodrigo.vivi@intel.com>
Subject: Re: [PATCH v5 09/13] drm/i915/icl: Program TA_TIMING_PARAM registers
Date: Wed, 12 Sep 2018 14:55:01 +0530 [thread overview]
Message-ID: <fbf84d1d-a86d-e6cd-bb5d-8a3767a5c507@intel.com> (raw)
In-Reply-To: <87tvmvdedm.fsf@intel.com>
On 9/12/2018 12:56 AM, Jani Nikula wrote:
> On Fri, 20 Jul 2018, "Chauhan, Madhav" <madhav.chauhan@intel.com> wrote:
>>> -----Original Message-----
>>> From: Ville Syrjälä [mailto:ville.syrjala@linux.intel.com]
>>> Sent: Thursday, July 19, 2018 9:51 PM
>>> To: Chauhan, Madhav <madhav.chauhan@intel.com>
>>> Cc: intel-gfx@lists.freedesktop.org; Nikula, Jani <jani.nikula@intel.com>;
>>> Zanoni, Paulo R <paulo.r.zanoni@intel.com>; Vivi, Rodrigo
>>> <rodrigo.vivi@intel.com>
>>> Subject: Re: [Intel-gfx] [PATCH v5 09/13] drm/i915/icl: Program
>>> TA_TIMING_PARAM registers
>>>
>>> On Tue, Jul 10, 2018 at 03:10:10PM +0530, Madhav Chauhan wrote:
>>>> This patch programs D-PHY timing parameters for the bus turn around
>>>> flow(in escape clocks) only if dsi link frequency <=800 MHz using
>>>> DPHY_TA_TIMING_PARAM and its identical register
>>> DSI_TA_TIMING_PARAM
>>>> (inside DSI Controller within the Display Core).
>>>>
>>>> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
>>>> ---
>>>> drivers/gpu/drm/i915/icl_dsi.c | 21 +++++++++++++++++++++
>>>> drivers/gpu/drm/i915/intel_dsi.h | 1 +
>>>> drivers/gpu/drm/i915/intel_dsi_vbt.c | 1 +
>>>> 3 files changed, 23 insertions(+)
>>>>
>>>> diff --git a/drivers/gpu/drm/i915/icl_dsi.c
>>>> b/drivers/gpu/drm/i915/icl_dsi.c index 832772d..8fd5284 100644
>>>> --- a/drivers/gpu/drm/i915/icl_dsi.c
>>>> +++ b/drivers/gpu/drm/i915/icl_dsi.c
>>>> @@ -302,6 +302,27 @@ static void gen11_dsi_setup_dphy_timings(struct
>>> intel_encoder *encoder)
>>>> I915_WRITE(DSI_DATA_TIMING_PARAM(port),
>>>> intel_dsi->dphy_data_lane_reg);
>>>> }
>>>> +
>>>> + /*
>>>> + * If DSI link operating at or below an 800 MHz,
>>>> + * TA_SURE should be override and programmed to
>>>> + * a value '0' inside TA_PARAM_REGISTERS otherwise
>>>> + * leave all fields at HW default values.
>>>> + */
>>>> + if (intel_dsi->bitrate_khz <= KHz(800)) {
>>> The KHz(800) confuses me. My brain thinks this value is 800 kHz when it's
>>> not. So I'd write it without the KHz() macro.
>> Ok. Initially I wrote without using KHz macro, but got comment to use KHz macro :)
> Did I? Oh well. Go with 800000.
Ok :)
>
> Please don't add additional state with intel_dsi->bitrate_khz when you
> can calculate the bitrate at any time. Add a function to do it if you
> like, and use it in both places.
Ok. But we will reusing this bitrate(same value) in multiple place.
Shouldn't
we cache it rather than calculating everytime??
Regards,
Madhav
>
> BR,
> Jani.
>
>
>> Regards,
>> Madhav
>>
>>>> + for_each_dsi_port(port, intel_dsi->ports) {
>>>> + tmp = I915_READ(DPHY_TA_TIMING_PARAM(port));
>>>> + tmp &= ~TA_SURE_TIME_MASK;
>>>> + tmp |= (TA_SURE_OVERRIDE | TA_SURE_TIME(0));
>>>> + I915_WRITE(DPHY_TA_TIMING_PARAM(port), tmp);
>>>> +
>>>> + /* shadow register inside display core */
>>>> + tmp = I915_READ(DSI_TA_TIMING_PARAM(port));
>>>> + tmp &= ~TA_SURE_TIME_MASK;
>>>> + tmp |= (TA_SURE_OVERRIDE | TA_SURE_TIME(0));
>>>> + I915_WRITE(DSI_TA_TIMING_PARAM(port), tmp);
>>>> + }
>>>> + }
>>>> }
>>>>
>>>> static void gen11_dsi_enable_port_and_phy(struct intel_encoder
>>>> *encoder) diff --git a/drivers/gpu/drm/i915/intel_dsi.h
>>>> b/drivers/gpu/drm/i915/intel_dsi.h
>>>> index 9fd8526..25e7396 100644
>>>> --- a/drivers/gpu/drm/i915/intel_dsi.h
>>>> +++ b/drivers/gpu/drm/i915/intel_dsi.h
>>>> @@ -101,6 +101,7 @@ struct intel_dsi {
>>>>
>>>> u16 init_count;
>>>> u32 pclk;
>>>> + u32 bitrate_khz;
>>>> u16 burst_mode_ratio;
>>>>
>>>> /* all delays in ms */
>>>> diff --git a/drivers/gpu/drm/i915/intel_dsi_vbt.c
>>>> b/drivers/gpu/drm/i915/intel_dsi_vbt.c
>>>> index 428290d..a9a98a4 100644
>>>> --- a/drivers/gpu/drm/i915/intel_dsi_vbt.c
>>>> +++ b/drivers/gpu/drm/i915/intel_dsi_vbt.c
>>>> @@ -589,6 +589,7 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi,
>>> u16 panel_id)
>>>> intel_dsi->pclk = pclk;
>>>>
>>>> bitrate = (pclk * bpp) / intel_dsi->lane_count;
>>>> + intel_dsi->bitrate_khz = bitrate;
>>>>
>>>> switch (intel_dsi->escape_clk_div) {
>>>> case 0:
>>>> --
>>>> 2.7.4
>>>>
>>>> _______________________________________________
>>>> Intel-gfx mailing list
>>>> Intel-gfx@lists.freedesktop.org
>>>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>>> --
>>> Ville Syrjälä
>>> Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2018-09-12 9:25 UTC|newest]
Thread overview: 63+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-07-10 9:40 [PATCH v5 00/13] ICELAKE DSI DRIVER Madhav Chauhan
2018-07-10 9:40 ` [PATCH v5 01/13] drm/i915/icl: Configure lane sequencing of combo phy transmitter Madhav Chauhan
2018-07-19 16:11 ` Ville Syrjälä
2018-07-19 18:35 ` Chauhan, Madhav
2018-07-27 11:57 ` Chauhan, Madhav
2018-09-11 17:46 ` Jani Nikula
2018-09-12 6:32 ` Madhav Chauhan
2018-09-10 12:20 ` Lisovskiy, Stanislav
2018-09-10 15:27 ` Madhav Chauhan
2018-09-11 8:08 ` Lisovskiy, Stanislav
2018-07-10 9:40 ` [PATCH v5 02/13] drm/i915/icl: DSI vswing programming sequence Madhav Chauhan
2018-09-06 14:01 ` [v5, " Kulkarni, Vandita
2018-09-10 7:43 ` Madhav Chauhan
2018-09-11 18:16 ` Jani Nikula
2018-09-12 6:34 ` Madhav Chauhan
2018-09-11 18:50 ` [PATCH v5 " Jani Nikula
2018-09-12 9:03 ` Madhav Chauhan
2018-09-12 9:10 ` Jani Nikula
2018-07-10 9:40 ` [PATCH v5 03/13] drm/i915/icl: Enable DDI Buffer Madhav Chauhan
2018-09-11 18:54 ` Jani Nikula
2018-09-12 9:06 ` Madhav Chauhan
2018-09-12 9:10 ` Jani Nikula
2018-07-10 9:40 ` [PATCH v5 04/13] drm/i915/icl: Define T_INIT_MASTER registers Madhav Chauhan
2018-09-11 19:18 ` Jani Nikula
2018-07-10 9:40 ` [PATCH v5 05/13] drm/i915/icl: Program " Madhav Chauhan
2018-09-11 19:17 ` Jani Nikula
2018-07-10 9:40 ` [PATCH v5 06/13] drm/i915/icl: Define data/clock lanes dphy timing registers Madhav Chauhan
2018-09-11 19:14 ` Jani Nikula
2018-09-12 9:11 ` Madhav Chauhan
2018-07-10 9:40 ` [PATCH v5 07/13] drm/i915/icl: Program DSI clock and data lane timing params Madhav Chauhan
2018-07-19 16:17 ` Ville Syrjälä
2018-07-10 9:40 ` [PATCH v5 08/13] drm/i915/icl: Define TA_TIMING_PARAM registers Madhav Chauhan
2018-09-11 19:23 ` Jani Nikula
2018-09-12 9:13 ` Madhav Chauhan
2018-07-10 9:40 ` [PATCH v5 09/13] drm/i915/icl: Program " Madhav Chauhan
2018-07-19 16:21 ` Ville Syrjälä
2018-07-20 8:08 ` Chauhan, Madhav
2018-09-11 19:26 ` Jani Nikula
2018-09-12 9:25 ` Madhav Chauhan [this message]
2018-09-12 9:39 ` Jani Nikula
2018-07-10 9:40 ` [PATCH v5 10/13] drm/i915/icl: Get DSI transcoder for a given port Madhav Chauhan
2018-07-10 9:40 ` [PATCH v5 11/13] drm/i915/icl: Add macros for MMIO of DSI transcoder registers Madhav Chauhan
2018-07-19 16:22 ` Ville Syrjälä
2018-07-20 8:55 ` Chauhan, Madhav
2018-09-12 9:36 ` Madhav Chauhan
2018-09-12 18:00 ` Ville Syrjälä
2018-09-14 6:12 ` Madhav Chauhan
2018-09-14 12:25 ` Ville Syrjälä
2018-09-14 13:06 ` Madhav Chauhan
2018-09-14 13:27 ` Madhav Chauhan
2018-09-14 13:41 ` Ville Syrjälä
2018-07-10 9:40 ` [PATCH v5 12/13] drm/i915/icl: Define TRANS_DSI_FUNC_CONF register Madhav Chauhan
2018-09-11 19:30 ` Jani Nikula
2018-09-12 9:35 ` Madhav Chauhan
2018-09-12 9:47 ` Jani Nikula
2018-07-10 9:40 ` [PATCH v5 13/13] drm/i915/icl: Configure DSI transcoders Madhav Chauhan
2018-07-10 10:46 ` ✗ Fi.CI.CHECKPATCH: warning for ICELAKE DSI DRIVER (rev5) Patchwork
2018-07-10 10:51 ` ✗ Fi.CI.SPARSE: " Patchwork
2018-07-10 11:04 ` ✓ Fi.CI.BAT: success " Patchwork
2018-07-10 16:28 ` ✓ Fi.CI.IGT: " Patchwork
2018-09-11 19:35 ` [PATCH v5 00/13] ICELAKE DSI DRIVER Jani Nikula
2018-09-12 6:16 ` Madhav Chauhan
2018-09-12 7:31 ` Jani Nikula
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=fbf84d1d-a86d-e6cd-bb5d-8a3767a5c507@intel.com \
--to=madhav.chauhan@intel.com \
--cc=intel-gfx@lists.freedesktop.org \
--cc=jani.nikula@intel.com \
--cc=paulo.r.zanoni@intel.com \
--cc=rodrigo.vivi@intel.com \
--cc=ville.syrjala@linux.intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).