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From: Jani Nikula <jani.nikula@linux.intel.com>
To: Ville Syrjala <ville.syrjala@linux.intel.com>,
	intel-gfx@lists.freedesktop.org
Cc: intel-xe@lists.freedesktop.org
Subject: Re: [PATCH 15/19] drm/i915/crt: Use IS0_R instead of VGA_MIS_W
Date: Tue, 09 Dec 2025 12:56:29 +0200	[thread overview]
Message-ID: <fc2341f6d4224ecba5f317cbe5f20380fc9e8d3d@intel.com> (raw)
In-Reply-To: <20251208182637.334-16-ville.syrjala@linux.intel.com>

On Mon, 08 Dec 2025, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Use the proper IS0_R name for the VGA input status register 0, instead
> of using the VGA_MIS_W alias which is meant for write accesses to the
> same address. Yes, VGA registers are weird.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_crt.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c
> index dedc26f6a2b2..6f216ba887bc 100644
> --- a/drivers/gpu/drm/i915/display/intel_crt.c
> +++ b/drivers/gpu/drm/i915/display/intel_crt.c
> @@ -738,7 +738,7 @@ intel_crt_load_detect(struct intel_crt *crt, enum pipe pipe)
>  		 * border color for Color info.
>  		 */
>  		intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(display, pipe));
> -		st00 = intel_vga_read(display, VGA_MIS_W, true);
> +		st00 = intel_vga_read(display, VGA_IS0_R, true);
>  		status = ((st00 & (1 << 4)) != 0) ?
>  			connector_status_connected :
>  			connector_status_disconnected;
> @@ -786,7 +786,7 @@ intel_crt_load_detect(struct intel_crt *crt, enum pipe pipe)
>  		do {
>  			count++;
>  			/* Read the ST00 VGA status register */
> -			st00 = intel_vga_read(display, VGA_MIS_W, true);
> +			st00 = intel_vga_read(display, VGA_IS0_R, true);
>  			if (st00 & (1 << 4))
>  				detect++;
>  		} while ((intel_de_read(display, PIPEDSL(display, pipe)) == dsl));

-- 
Jani Nikula, Intel

  reply	other threads:[~2025-12-09 10:56 UTC|newest]

Thread overview: 51+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-12-08 18:26 [PATCH 00/19] drm/i915/vga: Try to sort out the VGA decode mess Ville Syrjala
2025-12-08 18:26 ` [PATCH 01/19] drm/i915/vga: Register vgaarb client later Ville Syrjala
2025-12-09 10:23   ` Jani Nikula
2025-12-08 18:26 ` [PATCH 02/19] drm/i915/vga: Get rid of intel_vga_reset_io_mem() Ville Syrjala
2025-12-09 10:26   ` Jani Nikula
2025-12-08 18:26 ` [PATCH 03/19] drm/i915/power: Remove i915_power_well_desc::has_vga Ville Syrjala
2025-12-09 10:27   ` Jani Nikula
2025-12-08 18:26 ` [PATCH 04/19] drm/i915/vga: Extract intel_gmch_ctrl_reg() Ville Syrjala
2025-12-09 10:28   ` Jani Nikula
2025-12-08 18:26 ` [PATCH 05/19] drm/i915/vga: Don't touch VGA registers if VGA decode is fully disabled Ville Syrjala
2025-12-09 10:29   ` Jani Nikula
2025-12-08 18:26 ` [PATCH 06/19] drm/i915/vga: Clean up VGA registers even if VGA plane is disabled Ville Syrjala
2025-12-09 10:32   ` Jani Nikula
2025-12-08 18:26 ` [PATCH 07/19] drm/i915/vga: Avoid VGA arbiter during intel_vga_disable() for iGPUs Ville Syrjala
2025-12-09 10:35   ` Jani Nikula
2025-12-09 12:17     ` Ville Syrjälä
2025-12-08 18:26 ` [PATCH 08/19] drm/i915/vga: Stop trying to use GMCH_CTRL for VGA decode control Ville Syrjala
2025-12-09 10:39   ` Jani Nikula
2025-12-08 18:26 ` [PATCH 09/19] drm/i915/vga: Assert that VGA register accesses are going to the right GPU Ville Syrjala
2025-12-09 10:40   ` Jani Nikula
2025-12-08 18:26 ` [PATCH 10/19] drm/i915/de: Simplify intel_de_read8() Ville Syrjala
2025-12-09 10:47   ` Jani Nikula
2025-12-08 18:26 ` [PATCH 11/19] drm/i915/de: Add intel_de_write8() Ville Syrjala
2025-12-09 10:49   ` Jani Nikula
2025-12-08 18:26 ` [PATCH 12/19] drm/i915/vga: Introduce intel_vga_{read,write}() Ville Syrjala
2025-12-09 10:52   ` Jani Nikula
2025-12-08 18:26 ` [PATCH 13/19] drm/i915/vga: Use MMIO for VGA registers on pre-g4x Ville Syrjala
2025-12-09 10:53   ` Jani Nikula
2025-12-08 18:26 ` [PATCH 14/19] video/vga: Add VGA_IS0_R Ville Syrjala
2025-12-08 21:07   ` kernel test robot
2025-12-08 21:18   ` kernel test robot
2025-12-08 22:22   ` kernel test robot
2025-12-09  7:55   ` [PATCH v2 " Ville Syrjala
2025-12-09 10:55     ` Jani Nikula
2025-12-10 14:13   ` [PATCH " kernel test robot
2025-12-10 14:24   ` kernel test robot
2025-12-08 18:26 ` [PATCH 15/19] drm/i915/crt: Use IS0_R instead of VGA_MIS_W Ville Syrjala
2025-12-09 10:56   ` Jani Nikula [this message]
2025-12-08 18:26 ` [PATCH 16/19] drm/i915/crt: Extract intel_crt_sense_above_threshold() Ville Syrjala
2025-12-09 10:57   ` Jani Nikula
2025-12-08 18:26 ` [PATCH 17/19] drm/i915: Get rid of the INTEL_GMCH_CTRL alias Ville Syrjala
2025-12-09 10:58   ` Jani Nikula
2025-12-08 18:26 ` [PATCH 18/19] drm/i915: Clean up PCI config space reg defines Ville Syrjala
2025-12-09 11:00   ` Jani Nikula
2025-12-09 11:01   ` Jani Nikula
2025-12-08 18:26 ` [PATCH 19/19] drm/i915: Document the GMCH_CTRL register a bit Ville Syrjala
2025-12-09 11:03   ` Jani Nikula
2025-12-08 19:11 ` ✗ Fi.CI.BUILD: failure for drm/i915/vga: Try to sort out the VGA decode mess Patchwork
2025-12-09 11:31 ` ✗ i915.CI.BAT: failure for drm/i915/vga: Try to sort out the VGA decode mess (rev2) Patchwork
2025-12-10 19:14 ` ✓ i915.CI.BAT: success for drm/i915/vga: Try to sort out the VGA decode mess (rev3) Patchwork
2025-12-11  3:23 ` ✓ i915.CI.Full: " Patchwork

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