From mboxrd@z Thu Jan  1 00:00:00 1970
From: Robert Navarro <crshman@gmail.com>
Subject: Re: [PATCH] drm/i915: Increase WM memory latency values
	on SNB with high pixel clock
Date: Mon, 31 Mar 2014 18:29:51 +0000 (UTC)
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Runyan, Arthur J <arthur.j.runyan <at> intel.com> writes:

> 
> Please check the DRAM configuration for the systems that fail.  The higher 
latency is more likely with
> higher tRFC which is mainly found with 8 Gbit components.
> 

What other information do we need to get this included?

The DRAM config, is this something that I have to/should check? How do I get 
this information to you?