From mboxrd@z Thu Jan  1 00:00:00 1970
From: Takashi Iwai <tiwai@suse.de>
Subject: Re: Broken LVDS output at mode changes
Date: Thu, 29 Mar 2012 18:12:56 +0200
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To: Keith Packard <keithp@keithp.com>
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At Thu, 29 Mar 2012 08:07:05 -0700,
Keith Packard wrote:
> 
> On Thu, 29 Mar 2012 13:44:28 +0100, Chris Wilson <chris@chris-wilson.co.uk> wrote:
> 
> > In conjunction with bits Power Sequence Progress field and Power Cycle
> > Delay Active, this bit set to a one indicates that the panel is
> > currently powered up or is currently in the power down sequence and it
> > is unsafe to change the timing, port, and DPLL registers for the pipe or
> > transcoder that is assigned to the panel output.
> 
> The theory was that as we don't touch the DPLL and only modify the
> scaler, that the panel wouldn't care. I wonder what's confusing this one...

The strange thing is that, although you can recover the display by
turning off LVDS and on again once when the problem happens, but then
the display starts flickering.  And, the flickering continues even
after reboot on BIOS boot screen.  Even BIOS can't recover the problem
by itself, too, as it seems.  Then, keep the machine rest for long
time and boot up, now the problem is gone.

BTW, now I tested to disable LVDS unconditionally on different
platforms as Daniel suggested.  All worked fine, and I saw no
regressions.  Tested on IVY, SNB, ILK, GM45 and PineView.


thanks,

Takashi