From mboxrd@z Thu Jan  1 00:00:00 1970
From: Keith Packard <keithp@keithp.com>
Subject: Re: PCH reference clock cleanups
Date: Tue, 27 Sep 2011 09:54:45 -0700
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References: <yunbou6lxb4.fsf@aiko.keithp.com> <1317103906-4649-1-git-send-email-keithp@keithp.com> <e39f63$23ptfo@fmsmga002.fm.intel.com>
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To: Chris Wilson <chris@chris-wilson.co.uk>, Dave Airlie <airlied@redhat.com>
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On Tue, 27 Sep 2011 10:01:33 +0100, Chris Wilson <chris@chris-wilson.co.uk>=
 wrote:

> Oddly in the diagram SSC4 is given as a 100MHz clock that can be used for
> any output other than DP_A. However, the configuration register marks that
> as being a test-only mode.

Ok, it's all irrelevant -- the only configurations using anything other
than a fixed 120MHz were eDP and LVDS. LVDS used a value from the BIOS, whi=
ch is
presumably always 120MHz. eDP ignored the refclk and used fixed PLL
values.

So, yes, we can always set the refclk to 120MHz; the cases which matter
were using that value already.

=2D-=20
keith.packard@intel.com

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