Re: [PATCH 1/2] drm/i915/crt: Remove 0xa0 probe for CRT

[Keith Packard <keithp@keithp.com>]

[-- Attachment #1.1: Type: text/plain, Size: 1353 bytes --]

On Mon, 04 Apr 2011 16:29:55 +0100, Chris Wilson <chris@chris-wilson.co.uk> wrote:

> Yes. I'm saying that that the controller accepts a write to port 0xa0.

So it's the GMBUS controller itself then, I guess. Weird.

Let me see if I understand how it used to work and why fixing the GMBUS
reset causes it to break in this case.

In the distant past (pre-GMBUS)

 1) Some previous DDC transaction would fail, but without GMBUS
    this would not break the bus
 2) The 0xA0 transaction would fail as there wasn't anyone
    listening on the DDC bus.
 3) The 0x50 transaction would also fail, again because no-one
    was listening
 4) The monitor would be reported as disconnected.

In the recent past (post-GMBUS):

 1) Some previous DDC transaction would fail, wedging the GMBUS
 2) The 0xA0 transaction would then fail due to the GMBUS breakage
 3) The 0x50 transaction would also fail as the GMBUS was wedged
 4) The VGA port would be reported as disconnected

With the GMBUS reset:

 1) Some previous DDC transaction would fail, but the GMBUS would get
    reset
 2) The 0xA0 transaction would now succeed.
 3) The VGA port would be reported as connected.

Do we have any idea what ports the GMBUS controller is listening
internally for? And, whether this differs from chip to chip?

-- 
keith.packard@intel.com

[-- Attachment #1.2: Type: application/pgp-signature, Size: 189 bytes --]

[-- Attachment #2: Type: text/plain, Size: 159 bytes --]

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx