From mboxrd@z Thu Jan 1 00:00:00 1970 From: Keith Packard Subject: Re: [PATCH 1/2] drm/i915/crt: Remove 0xa0 probe for CRT Date: Mon, 04 Apr 2011 09:26:20 -0700 Message-ID: References: <1301898405-6999-1-git-send-email-chris@chris-wilson.co.uk> <849307$cab831@azsmga001.ch.intel.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============0050652516==" Return-path: Received: from keithp.com (home.keithp.com [63.227.221.253]) by gabe.freedesktop.org (Postfix) with ESMTP id 138229E710 for ; Mon, 4 Apr 2011 09:26:32 -0700 (PDT) In-Reply-To: <849307$cab831@azsmga001.ch.intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Chris Wilson , intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org --===============0050652516== Content-Type: multipart/signed; boundary="=-=-="; micalg=pgp-sha1; protocol="application/pgp-signature" --=-=-= Content-Transfer-Encoding: quoted-printable On Mon, 04 Apr 2011 16:29:55 +0100, Chris Wilson = wrote: > Yes. I'm saying that that the controller accepts a write to port 0xa0. So it's the GMBUS controller itself then, I guess. Weird. Let me see if I understand how it used to work and why fixing the GMBUS reset causes it to break in this case. In the distant past (pre-GMBUS) 1) Some previous DDC transaction would fail, but without GMBUS this would not break the bus 2) The 0xA0 transaction would fail as there wasn't anyone listening on the DDC bus. 3) The 0x50 transaction would also fail, again because no-one was listening 4) The monitor would be reported as disconnected. In the recent past (post-GMBUS): 1) Some previous DDC transaction would fail, wedging the GMBUS 2) The 0xA0 transaction would then fail due to the GMBUS breakage 3) The 0x50 transaction would also fail as the GMBUS was wedged 4) The VGA port would be reported as disconnected With the GMBUS reset: 1) Some previous DDC transaction would fail, but the GMBUS would get reset 2) The 0xA0 transaction would now succeed. 3) The VGA port would be reported as connected. Do we have any idea what ports the GMBUS controller is listening internally for? And, whether this differs from chip to chip? =2D-=20 keith.packard@intel.com --=-=-= Content-Type: application/pgp-signature -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iD8DBQFNmfEsQp8BWwlsTdMRAhZAAKC2TRGIWm3Y86pKN58awZJExDB01QCgwXeK DUCrwyS21t+EYWEdm/Yan3o= =oxMu -----END PGP SIGNATURE----- --=-=-=-- --===============0050652516== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx --===============0050652516==--