From mboxrd@z Thu Jan 1 00:00:00 1970 From: Keith Packard Subject: Re: [PATCH] drm/i915: add missing "break" Date: Thu, 22 Sep 2011 21:35:51 -0700 Message-ID: References: <1316715222-2815-1-git-send-email-przanoni@gmail.com> <20110923081315.7a327fcd@jbarnes-x220> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============1318953548==" Return-path: Received: from keithp.com (home.keithp.com [63.227.221.253]) by gabe.freedesktop.org (Postfix) with ESMTP id 5F8FB9EB6F for ; Thu, 22 Sep 2011 21:35:58 -0700 (PDT) In-Reply-To: <20110923081315.7a327fcd@jbarnes-x220> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Jesse Barnes Cc: intel-gfx@lists.freedesktop.org, Paulo Zanoni List-Id: intel-gfx@lists.freedesktop.org --===============1318953548== Content-Type: multipart/signed; boundary="=-=-="; micalg=pgp-sha1; protocol="application/pgp-signature" --=-=-= Content-Transfer-Encoding: quoted-printable On Fri, 23 Sep 2011 08:13:15 +0530, Jesse Barnes = wrote: > I think it depends on the platform. On some, enabling SSC may actually > create more noise than not for some components (not that I've run the > EMF calculations...). So, why is the MBA EFI code enabling SSC while the VBT table says not to use it? It's all mysterious to me. > I don't have this code in my tree though... is this the patch I sent > awhile back? I thought it broke external outputs too? The last time > we touched this we broke the dual head case (a config change caused one > head to go blank), did you test that? You sent two pieces, I think; the second one tried to turn unused clocks off and that broke stuff. Which is understandable given that it was only looking at one CRTC when doing the global configuration. > What I don't understand about the refclk code is that we should be able > to leave everything enabled and just select the right clock source in > the DPLL_SEL bits. But that doesn't seem to help the wavy VGA bug, > since in that case I think we're explicitly choosing the non-SSC clock > and we still get waviness. We don't have any hardware anywhere which exhibits this problem, do we? Getting hold of some would let us poke at it. > I *think* the code you changed is ok; just needs lots of testing and > verification that the SSC bits are set like we expect as we change > configurations. I like the "has_panel" cleanup too; previous versions > of this code had is_lvds || is_edp && pch_edp etc sprinkled all over. Yeah, it's longer, but I think it's more readable now. My big concern is that we're guessing which pipes will use SSC in this function and then computing which pipes actually use SSC separately. I think we should figure out which pipes want to use SSC and then go set the refclks. as needed. =2D-=20 keith.packard@intel.com --=-=-= Content-Type: application/pgp-signature -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iD8DBQFOfAyoQp8BWwlsTdMRAolnAKDMcAnniqWPgqNWSRHY03+5EueEogCeNe1T HPBJv4q5g/M0702sEE6anCg= =jqbc -----END PGP SIGNATURE----- --=-=-=-- --===============1318953548== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx --===============1318953548==--