From mboxrd@z Thu Jan 1 00:00:00 1970 From: Keith Packard Subject: [PATCH] drm/i915: Fix restore of 965 fence regs since the register tracing change. Date: Thu, 18 Nov 2010 11:47:12 +0800 Message-ID: References: <1290045900-4012-1-git-send-email-eric@anholt.net> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============0493828939==" Return-path: Received: from keithp.com (home.keithp.com [63.227.221.253]) by gabe.freedesktop.org (Postfix) with ESMTP id 7196B9ECDD for ; Wed, 17 Nov 2010 19:47:18 -0800 (PST) In-Reply-To: <1290045900-4012-1-git-send-email-eric@anholt.net> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Eric Anholt , intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org --===============0493828939== Content-Type: multipart/signed; boundary="=-=-="; micalg=pgp-sha1; protocol="application/pgp-signature" --=-=-= Content-Transfer-Encoding: quoted-printable We were reading our 64-bit value in I915_READ64 and returning 32 bits of it. The restoration of fence regs at resume then had a zero end value, and the fence had no effect. Version 2: Split register access functions into per-size versions Sharing code between different sizes seemed reasonable when we only needed a single copy, but as 64-bit access requires its own version, it makes sense to just split them out for each size. Signed-off-by: Eric Anholt Signed-off-by: Keith Packard =2D-- On Thu, 18 Nov 2010 10:05:00 +0800, Eric Anholt wrote: > #define I915_READ8(reg) i915_read(dev_priv, (reg), 1) > #define I915_WRITE8(reg, val) i915_write(dev_priv, (reg), (val), 1) > #define I915_WRITE64(reg, val) i915_write(dev_priv, (reg), (val), 8) > -#define I915_READ64(reg) i915_read(dev_priv, (reg), 8) > +#define I915_READ64(reg) i915_read64(dev_priv, (reg)) Now that we've got two functions for this, it seems like it would be better to just create per-size versions in both directions, otherwise changes to the 8/16/32 bit version are unlikely to get propagated to the 64-bit version. drivers/gpu/drm/i915/i915_drv.h | 106 ++++++++++++++++++++++-------------= --- 1 files changed, 61 insertions(+), 45 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_dr= v.h index 73a41f7..f83e712 100644 =2D-- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1237,14 +1237,14 @@ extern void intel_overlay_print_error_state(struct = seq_file *m, struct intel_ove LOCK_TEST_WITH_RETURN(dev, file_priv); \ } while (0) =20 =2D#define I915_READ(reg) i915_read(dev_priv, (reg), 4) =2D#define I915_WRITE(reg, val) i915_write(dev_priv, (reg), (val), 4) =2D#define I915_READ16(reg) i915_read(dev_priv, (reg), 2) =2D#define I915_WRITE16(reg, val) i915_write(dev_priv, (reg), (val), 2) =2D#define I915_READ8(reg) i915_read(dev_priv, (reg), 1) =2D#define I915_WRITE8(reg, val) i915_write(dev_priv, (reg), (val), 1) =2D#define I915_WRITE64(reg, val) i915_write(dev_priv, (reg), (val), 8) =2D#define I915_READ64(reg) i915_read(dev_priv, (reg), 8) +#define I915_READ(reg) i915_read32(dev_priv, (reg)) +#define I915_WRITE(reg, val) i915_write32(dev_priv, (reg), (val)) +#define I915_READ16(reg) i915_read16(dev_priv, (reg)) +#define I915_WRITE16(reg, val) i915_write16(dev_priv, (reg), (val)) +#define I915_READ8(reg) i915_read8(dev_priv, (reg)) +#define I915_WRITE8(reg, val) i915_write8(dev_priv, (reg), (val)) +#define I915_WRITE64(reg, val) i915_write64(dev_priv, (reg), (val)) +#define I915_READ64(reg) i915_read64(dev_priv, (reg)) =20 #define I915_READ_NOTRACE(reg) readl(dev_priv->regs + (reg)) #define I915_WRITE_NOTRACE(reg, val) writel(val, dev_priv->regs + (reg)) @@ -1254,27 +1254,32 @@ extern void intel_overlay_print_error_state(struct = seq_file *m, struct intel_ove #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg) #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg) =20 =2Dstatic inline u32 i915_read(struct drm_i915_private *dev_priv, u32 reg, = int len) +static inline u8 i915_read8(struct drm_i915_private *dev_priv, u32 reg) { =2D u64 val =3D 0; =2D =2D switch (len) { =2D case 8: =2D val =3D readq(dev_priv->regs + reg); =2D break; =2D case 4: =2D val =3D readl(dev_priv->regs + reg); =2D break; =2D case 2: =2D val =3D readw(dev_priv->regs + reg); =2D break; =2D case 1: =2D val =3D readb(dev_priv->regs + reg); =2D break; =2D } =2D trace_i915_reg_rw('R', reg, val, len); =2D =2D return val; + u8 val =3D readb(dev_priv->regs + reg); + trace_i915_reg_rw('R', reg, val, 1); + return val; +} + +static inline u16 i915_read16(struct drm_i915_private *dev_priv, u32 reg) +{ + u16 val =3D readw(dev_priv->regs + reg); + trace_i915_reg_rw('R', reg, val, 2); + return val; +} + +static inline u32 i915_read32(struct drm_i915_private *dev_priv, u32 reg) +{ + u32 val =3D readl(dev_priv->regs + reg); + trace_i915_reg_rw('R', reg, val, 4); + return val; +} + +static inline u64 i915_read64(struct drm_i915_private *dev_priv, u32 reg) +{ + u64 val =3D readq(dev_priv->regs + reg); + trace_i915_reg_rw('R', reg, val, 8); + return val; } =20 /* On SNB platform, before reading ring registers forcewake bit @@ -1295,24 +1300,35 @@ static inline u32 i915_safe_read(struct drm_i915_pr= ivate *dev_priv, u32 reg) } =20 static inline void =2Di915_write(struct drm_i915_private *dev_priv, u32 reg, u64 val, int len) +i915_write8(struct drm_i915_private *dev_priv, u32 reg, u8 val) +{ + /* Trace down the write operation before the real write */ + trace_i915_reg_rw('W', reg, val, 1); + writeb(val, dev_priv->regs + reg); +} + +static inline void +i915_write16(struct drm_i915_private *dev_priv, u32 reg, u16 val) +{ + /* Trace down the write operation before the real write */ + trace_i915_reg_rw('W', reg, val, 2); + writew(val, dev_priv->regs + reg); +} + +static inline void +i915_write32(struct drm_i915_private *dev_priv, u32 reg, u32 val) +{ + /* Trace down the write operation before the real write */ + trace_i915_reg_rw('W', reg, val, 4); + writel(val, dev_priv->regs + reg); +} + +static inline void +i915_write64(struct drm_i915_private *dev_priv, u32 reg, u64 val) { =2D /* Trace down the write operation before the real write */ =2D trace_i915_reg_rw('W', reg, val, len); =2D switch (len) { =2D case 8: =2D writeq(val, dev_priv->regs + reg); =2D break; =2D case 4: =2D writel(val, dev_priv->regs + reg); =2D break; =2D case 2: =2D writew(val, dev_priv->regs + reg); =2D break; =2D case 1: =2D writeb(val, dev_priv->regs + reg); =2D break; =2D } + /* Trace down the write operation before the real write */ + trace_i915_reg_rw('W', reg, val, 8); + writeq(val, dev_priv->regs + reg); } =20 #define BEGIN_LP_RING(n) \ =2D-=20 1.7.2.3 =2D-=20 keith.packard@intel.com --=-=-= Content-Type: application/pgp-signature -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.10 (GNU/Linux) iD8DBQFM5KHBQp8BWwlsTdMRAnWUAKC71ToFGOYWNwhGOS3am+tjh0Y71ACfSrJ/ 7PbMhEmhAuc+tFn907VGFSo= =eo9S -----END PGP SIGNATURE----- --=-=-=-- --===============0493828939== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx --===============0493828939==--