From mboxrd@z Thu Jan 1 00:00:00 1970 From: Tony Nguyen Date: Fri, 15 May 2020 17:51:21 -0700 Subject: [Intel-wired-lan] [PATCH S45 15/15] ice: Update ICE_PHY_TYPE_HIGH_MAX_INDEX value In-Reply-To: <20200516005121.4963-1-anthony.l.nguyen@intel.com> References: <20200516005121.4963-1-anthony.l.nguyen@intel.com> Message-ID: <20200516005121.4963-15-anthony.l.nguyen@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: intel-wired-lan@osuosl.org List-ID: From: Chinh T Cao As currently, we are supporting only 5 PHY_SPEEDs for phy_type_high. Thus, we should adjust the value of ICE_PHY_TYPE_HIGH_MAX_INDEX to 5. Signed-off-by: Chinh T Cao --- drivers/net/ethernet/intel/ice/ice_adminq_cmd.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ethernet/intel/ice/ice_adminq_cmd.h b/drivers/net/ethernet/intel/ice/ice_adminq_cmd.h index 1d939ff4bf99..bba47f11e546 100644 --- a/drivers/net/ethernet/intel/ice/ice_adminq_cmd.h +++ b/drivers/net/ethernet/intel/ice/ice_adminq_cmd.h @@ -975,7 +975,7 @@ struct ice_aqc_get_phy_caps { #define ICE_PHY_TYPE_HIGH_100G_CAUI2 BIT_ULL(2) #define ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC BIT_ULL(3) #define ICE_PHY_TYPE_HIGH_100G_AUI2 BIT_ULL(4) -#define ICE_PHY_TYPE_HIGH_MAX_INDEX 19 +#define ICE_PHY_TYPE_HIGH_MAX_INDEX 5 struct ice_aqc_get_phy_caps_data { __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */ -- 2.20.1