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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=k20201202 header.b=GXdurLDe Subject: Re: [Intel-wired-lan] [PATCH] igc: Mask replay rollover/timeout errors in I225_LMVP X-BeenThere: intel-wired-lan@osuosl.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Wired Ethernet Linux Kernel Driver Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paul Menzel , Rajat Khandelwal , Leon Romanovsky , "davem@davemloft.net" , "netdev@vger.kernel.org" , "Mushayev, Nikolay" , "Brandeburg, Jesse" , "linux-kernel@vger.kernel.org" , "kuba@kernel.org" , "edumazet@google.com" , "pabeni@redhat.com" , "Nguyen, Anthony L" , "linux-pci@vger.kernel.org" , Bjorn Helgaas , "Ruinskiy, Dima" , "Efrati, Nir" , "intel-wired-lan@lists.osuosl.org" Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: intel-wired-lan-bounces@osuosl.org Sender: "Intel-wired-lan" On Tue, Jan 03, 2023 at 06:58:36AM +0000, Khandelwal, Rajat wrote: > ... > The reason I masked inherently is I witnessed a function > netxen_mask_aer_correctable() inside > net/ethernet/qlogic/netxen/netxen_nic_main.c, which masks the > correctable errors in the corresponding PCIe device. In my opinion, netxen_mask_aer_correctable() should not exist. The PCI core should own the PCI_ERR_COR_MASK register. netxen_mask_aer_correctable() was added by dce87b960cf4 ("netxen: mask correctable error") with the note that it is a "HW workaround." Maybe it covers up some hardware defect in the device, although it doesn't include any evidence of this. But if we do actually need it, I would rather have the driver set a quirk bit that the PCI core can use to mask correctable errors so the AER configuration is all in one place. Bjorn _______________________________________________ Intel-wired-lan mailing list Intel-wired-lan@osuosl.org https://lists.osuosl.org/mailman/listinfo/intel-wired-lan