From: Karen Ostrowska <karen.ostrowska@intel.com>
To: intel-wired-lan@lists.osuosl.org
Cc: Karen Ostrowska <karen.ostrowska@intel.com>
Subject: [Intel-wired-lan] [PATCH net v1] ice: Fix DSCP PFC TLV creation
Date: Wed, 25 Jan 2023 17:01:49 +0100 [thread overview]
Message-ID: <20230125160149.1899331-1-karen.ostrowska@intel.com> (raw)
From: Dave Ertman <david.m.ertman@intel.com>
When creating the TLV to send to the FW for configuring DSCP
mode PFC, the PFCENABLE field was being masked with a 4 bit
mask (0xF), but this is an 8 bit bitmask for enabled classes
for PFC. This means that traffic classes 4-7 could not be
enabled for PFC.
Remove the mask completely, as it is not necessary, as we are
assigning 8bits to an 8 bit field.
Fixes: 2a87bd73e50d("ice: Add DSCP support")
Signed-off-by: Dave Ertman <david.m.ertman@intel.com>
Signed-off-by: Karen Ostrowska <karen.ostrowska@intel.com>
---
drivers/net/ethernet/intel/ice/ice_dcb.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/intel/ice/ice_dcb.c b/drivers/net/ethernet/intel/ice/ice_dcb.c
index 6be02f9b0b8c..789b99963910 100644
--- a/drivers/net/ethernet/intel/ice/ice_dcb.c
+++ b/drivers/net/ethernet/intel/ice/ice_dcb.c
@@ -1372,7 +1372,7 @@ ice_add_dscp_pfc_tlv(struct ice_lldp_org_tlv *tlv, struct ice_dcbx_cfg *dcbcfg)
tlv->ouisubtype = htonl(ouisubtype);
buf[0] = dcbcfg->pfc.pfccap & 0xF;
- buf[1] = dcbcfg->pfc.pfcena & 0xF;
+ buf[1] = dcbcfg->pfc.pfcena;
}
/**
--
2.31.1
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next reply other threads:[~2023-01-25 16:38 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-01-25 16:01 Karen Ostrowska [this message]
2023-01-25 23:36 ` [Intel-wired-lan] [PATCH net v1] ice: Fix DSCP PFC TLV creation Tony Nguyen
2023-01-27 17:57 ` Ertman, David M
2023-01-26 8:18 ` Paul Menzel
-- strict thread matches above, loose matches on Subject: below --
2023-01-27 13:24 Karen Ostrowska
2023-01-31 21:40 ` Tony Nguyen
2023-03-06 11:21 ` G, GurucharanX
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