[Intel-wired-lan] [PATCH iwl-next 2/4] ice: Clean the main timer command register after use

[Jacob Keller <jacob.e.keller@intel.com>]

From: Sergey Temerkhanov <sergey.temerkhanov@intel.com>

When performing certain commands on the ice hardware to program the clock,
the driver must use the GLTSYN_CMD register to prepare the main timer. In
addition, each PHY that is being operated on must have its own command
register programmed. The driver then tells hardware to synchronously
execute all commands by writing to GLTSYN_CMD_EXEC. In some cases, the
driver wants to execute a command on a single port, without affecting the
main timer. In this case, the GLTSYN_CMD register must be cleared.

Introduce and use ice_ptp_clean_cmd() to ensure that we properly zero the
GLTSYN_CMD after each command execution. This ensures that we do not
accidentally perform a command on the main timer unexpectedly.

Signed-off-by: Sergey Temerkhanov <sergey.temerkhanov@intel.com>
Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
---
 drivers/net/ethernet/intel/ice/ice_ptp_hw.c | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c b/drivers/net/ethernet/intel/ice/ice_ptp_hw.c
index c82eb2869b33..87b409ce6991 100644
--- a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c
+++ b/drivers/net/ethernet/intel/ice/ice_ptp_hw.c
@@ -150,6 +150,18 @@ static void ice_ptp_exec_tmr_cmd(struct ice_hw *hw)
 	ice_flush(hw);
 }
 
+/**
+ * ice_ptp_clean_cmd - Clean the timer command register
+ * @hw: pointer to HW struct
+ *
+ * Zero out the GLTSYN_CMD to avoid any residual command execution.
+ */
+static void ice_ptp_clean_cmd(struct ice_hw *hw)
+{
+	wr32(hw, GLTSYN_CMD, 0);
+	ice_flush(hw);
+}
+
 /* E822 family functions
  *
  * The following functions operate on the E822 family of devices.
@@ -2182,6 +2194,7 @@ ice_read_phy_and_phc_time_e822(struct ice_hw *hw, u8 port, u64 *phy_time,
 
 	/* Issue the sync to start the ICE_PTP_READ_TIME capture */
 	ice_ptp_exec_tmr_cmd(hw);
+	ice_ptp_clean_cmd(hw);
 
 	/* Read the captured PHC time from the shadow time registers */
 	zo = rd32(hw, GLTSYN_SHTIME_0(tmr_idx));
@@ -2254,6 +2267,7 @@ static int ice_sync_phy_timer_e822(struct ice_hw *hw, u8 port)
 
 	/* Issue the sync to activate the time adjustment */
 	ice_ptp_exec_tmr_cmd(hw);
+	ice_ptp_clean_cmd(hw);
 
 	/* Re-capture the timer values to flush the command registers and
 	 * verify that the time was properly adjusted.
@@ -2344,6 +2358,7 @@ int ice_start_phy_timer_e822(struct ice_hw *hw, u8 port)
 	u8 tmr_idx;
 	int err;
 
+	ice_ptp_clean_cmd(hw);
 	tmr_idx = ice_get_ptp_src_clock_index(hw);
 
 	err = ice_stop_phy_timer_e822(hw, port, false);
@@ -2957,6 +2972,7 @@ static int ice_ptp_tmr_cmd(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd)
 	 * commands synchronously
 	 */
 	ice_ptp_exec_tmr_cmd(hw);
+	ice_ptp_clean_cmd(hw);
 
 	return 0;
 }
-- 
2.41.0.1.g9857a21e0017.dirty

_______________________________________________
Intel-wired-lan mailing list
Intel-wired-lan@osuosl.org
https://lists.osuosl.org/mailman/listinfo/intel-wired-lan