From: Anton Nadezhdin <anton.nadezhdin@intel.com>
To: intel-wired-lan@lists.osuosl.org
Cc: netdev@vger.kernel.org, anthony.l.nguyen@intel.com,
przemyslaw.kitszel@intel.com, richardcochran@gmail.com,
Jacob Keller <jacob.e.keller@intel.com>,
Karol Kolacinski <karol.kolacinski@intel.com>,
Milena Olech <milena.olech@intel.com>,
Anton Nadezhdin <anton.nadezhdin@intel.com>
Subject: [Intel-wired-lan] [PATCH iwl-next v2 4/5] ice: check low latency PHY timer update firmware capability
Date: Tue, 10 Dec 2024 09:22:08 -0500 [thread overview]
Message-ID: <20241210142333.320515-5-anton.nadezhdin@intel.com> (raw)
In-Reply-To: <20241210142333.320515-1-anton.nadezhdin@intel.com>
From: Jacob Keller <jacob.e.keller@intel.com>
Newer versions of firmware support programming the PHY timer via the low
latency interface exposed over REG_LL_PROXY_L and REG_LL_PROXY_H. Add
support for checking the device capabilities for this feature.
Co-developed-by: Karol Kolacinski <karol.kolacinski@intel.com>
Signed-off-by: Karol Kolacinski <karol.kolacinski@intel.com>
Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
Reviewed-by: Milena Olech <milena.olech@intel.com>
Signed-off-by: Anton Nadezhdin <anton.nadezhdin@intel.com>
---
drivers/net/ethernet/intel/ice/ice_common.c | 3 +++
drivers/net/ethernet/intel/ice/ice_type.h | 2 ++
2 files changed, 5 insertions(+)
diff --git a/drivers/net/ethernet/intel/ice/ice_common.c b/drivers/net/ethernet/intel/ice/ice_common.c
index faba09b9d880..d23f413740c4 100644
--- a/drivers/net/ethernet/intel/ice/ice_common.c
+++ b/drivers/net/ethernet/intel/ice/ice_common.c
@@ -2507,6 +2507,7 @@ ice_parse_1588_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p,
info->ts_ll_read = ((number & ICE_TS_LL_TX_TS_READ_M) != 0);
info->ts_ll_int_read = ((number & ICE_TS_LL_TX_TS_INT_READ_M) != 0);
+ info->ll_phy_tmr_update = ((number & ICE_TS_LL_PHY_TMR_UPDATE_M) != 0);
info->ena_ports = logical_id;
info->tmr_own_map = phys_id;
@@ -2529,6 +2530,8 @@ ice_parse_1588_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p,
info->ts_ll_read);
ice_debug(hw, ICE_DBG_INIT, "dev caps: ts_ll_int_read = %u\n",
info->ts_ll_int_read);
+ ice_debug(hw, ICE_DBG_INIT, "dev caps: ll_phy_tmr_update = %u\n",
+ info->ll_phy_tmr_update);
ice_debug(hw, ICE_DBG_INIT, "dev caps: ieee_1588 ena_ports = %u\n",
info->ena_ports);
ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr_own_map = %u\n",
diff --git a/drivers/net/ethernet/intel/ice/ice_type.h b/drivers/net/ethernet/intel/ice/ice_type.h
index 5f3af5f3d2cb..25d6dad1852b 100644
--- a/drivers/net/ethernet/intel/ice/ice_type.h
+++ b/drivers/net/ethernet/intel/ice/ice_type.h
@@ -369,6 +369,7 @@ struct ice_ts_func_info {
#define ICE_TS_TMR1_ENA_M BIT(26)
#define ICE_TS_LL_TX_TS_READ_M BIT(28)
#define ICE_TS_LL_TX_TS_INT_READ_M BIT(29)
+#define ICE_TS_LL_PHY_TMR_UPDATE_M BIT(30)
struct ice_ts_dev_info {
/* Device specific info */
@@ -383,6 +384,7 @@ struct ice_ts_dev_info {
u8 tmr1_ena;
u8 ts_ll_read;
u8 ts_ll_int_read;
+ u8 ll_phy_tmr_update;
};
#define ICE_NAC_TOPO_PRIMARY_M BIT(0)
--
2.42.0
next prev parent reply other threads:[~2024-12-10 8:25 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-12-10 14:22 [Intel-wired-lan] [PATCH iwl-next v2 0/5] ice: implement low latency PHY timer updates Anton Nadezhdin
2024-12-10 14:22 ` [Intel-wired-lan] [PATCH iwl-next v2 1/5] ice: use rd32_poll_timeout_atomic in ice_read_phy_tstamp_ll_e810 Anton Nadezhdin
2024-12-10 14:22 ` [Intel-wired-lan] [PATCH iwl-next v2 2/5] ice: rename TS_LL_READ* macros to REG_LL_PROXY_H_* Anton Nadezhdin
2024-12-10 14:22 ` [Intel-wired-lan] [PATCH iwl-next v2 3/5] ice: add lock to protect low latency interface Anton Nadezhdin
2024-12-10 14:22 ` Anton Nadezhdin [this message]
2024-12-10 14:22 ` [Intel-wired-lan] [PATCH iwl-next v2 5/5] ice: implement low latency PHY timer updates Anton Nadezhdin
2024-12-12 23:42 ` [Intel-wired-lan] [PATCH iwl-next v2 0/5] " Tony Nguyen
-- strict thread matches above, loose matches on Subject: below --
2024-12-16 14:53 Anton Nadezhdin
2024-12-16 14:53 ` [Intel-wired-lan] [PATCH iwl-next v2 4/5] ice: check low latency PHY timer update firmware capability Anton Nadezhdin
2024-12-23 17:09 ` Rinitha, SX
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20241210142333.320515-5-anton.nadezhdin@intel.com \
--to=anton.nadezhdin@intel.com \
--cc=anthony.l.nguyen@intel.com \
--cc=intel-wired-lan@lists.osuosl.org \
--cc=jacob.e.keller@intel.com \
--cc=karol.kolacinski@intel.com \
--cc=milena.olech@intel.com \
--cc=netdev@vger.kernel.org \
--cc=przemyslaw.kitszel@intel.com \
--cc=richardcochran@gmail.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox